设计一段verilog代码及testbench测试文件，要求将15×10的二进制矩阵和7个10-bit列向量相乘，分别比较这7个输出结果中的系数，选出最大系数对应的矩阵中的基向量输出。

以下是给出的Verilog代码及testbench测试文件：

Verilog代码：

module matrix_multiplier(
    input [14:0] matrix[9:0],
    input [9:0] vectors[6:0],
    output logic [14:0] selected_vector);

    logic [69:0] results;
    logic [9:0] max_index;
  
    always_comb begin
        results = 0;
        for (int i = 0; i < 7; i++) begin
            for (int j = 0; j < 15; j++) begin
                results[i*10 + j] = vectors[i] * matrix[j][9:0];
            end
        end
    end
  
    always_comb begin
        max_index = 0;
        for (int i = 0; i < 7; i++) begin
            if (results[i*10 +: 10] > results[max_index*10 +: 10]) begin
                max_index = i;
            end
        end
    end
  
    assign selected_vector = matrix[max_index];
  
endmodule

testbench测试文件：

module matrix_multiplier_tb;

    reg [14:0] matrix[9:0];
    reg [9:0] vectors[6:0];
    wire [14:0] selected_vector;
  
    matrix_multiplier dut(
        .matrix(matrix),
        .vectors(vectors),
        .selected_vector(selected_vector)
    );
  
    integer i, j;
  
    initial begin
        // Initialize matrix
        for (i = 0; i < 10; i++) begin
            for (j = 0; j < 15; j++) begin
                matrix[i][j] = $random;
            end
        end
      
        // Initialize vectors
        for (i = 0; i < 7; i++) begin
            vectors[i] = $random;
        end
      
        #10;
      
        // Select the max index
        $display("Selected vector: %b", selected_vector);
    end
  
endmodule