Infineon收购后S29GL064S：64Mbit Flash Memory数据手册

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S29GL064S数据手册是来自 Cypress Semiconductor Corporation（现已被 Infineon Technologies Company 收购）的一款重要存储芯片产品。这款64-Mbit（8M字节）的Flash Memory，工作电压为3.0V，专为那些寻求高效能、低功耗以及灵活性的系统设计者而开发。其核心采用CMOS技术，具有3.0伏特电压供应，这意味着它可以在单一电源环境下运作，这对于简化电路设计和降低能耗非常有利。该芯片的主要特点包括： 1. 通用I/O架构：S29GL064S的优势在于其灵活的I/O接口设计，可以适应多种应用环境，并支持多种外设通信协议，提高了系统的扩展性和兼容性。 2. 单电源操作：由于其能够在3.0V的工作电压下运行，这意味着在设计电路时无需额外考虑电源管理，降低了系统复杂性和成本。 3. 制造工艺：作为Cypress的产品，它采用了先进的制造技术，保证了高可靠性和稳定性，同时保持了小型化和高性能的特点。 4. 文档连续性与支持：尽管Infineon收购了Cypress，但该产品的文档内容保持一致，以确保用户能够延续之前的技术支持和了解。Infineon承诺将继续为新老客户提供服务，并在必要时进行文档更新，所有更改都会记录在文档历史页面上。 5. 订单持续可用性：尽管公司名称改变，但订购部分仍然沿用原有的型号，用户可以直接参考数据手册中的列表进行订购。最后，文档编号为001-98286 Rev.*H，最后一次修订日期为2018年8月3日。对于需要使用这款存储芯片的工程师或设计者来说，这份数据手册提供了详尽的规格参数、电气特性、引脚图以及典型应用示例，帮助他们优化设计并充分利用S29GL064S的功能。总体而言，S29GL064S是一款实用且可靠的3.0V Flash Memory解决方案，适合对存储容量和性能有较高要求的应用场景。

Document Number: 001-98286 Rev. *H Page 15 of 106

S29GL064S

8.2 Requirements for Reading Array Data

All memories require access time to output array data. In a read operation, data is read from one memory location at a time.

Addresses are presented to the device in random order, and the propagation delay through the device causes the data on its outputs

to arrive with the address on its inputs.

The device defaults to reading array data after device power-up or hardware reset. To read data from the memory array, the system

must first assert a valid address on Amax–A0, while driving OE# and CE# to V

. WE# must remain at V

. Data will appear on

DQ15–DQ0 after address access time (t

ACC

), which is equal to the delay from stable addresses to valid output data. The OE# signal

must be driven to V

. Data is output on DQ15-DQ0 pins after the access time (t

) has elapsed from the falling edge of OE#.

See Reading Array Data on page 30 for more information. Refer to Table 67 on page 84 and Table 68 on page 85 for timing

specifications and the timing diagram. Refer to Table 59 on page 77 and Table 60 on page 78 for the active current specification on

reading array data.

8.2.1 Page Mode Read

The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides

faster read access speed for random locations within a page. The page size of the device is 8 words / 16 bytes. The appropriate

page is selected by the higher address bits A(max)–A3. Address bits A2–A0 in word mode (A2–A-1 in byte mode) determine the

specific word within a page. This is an asynchronous operation; the microprocessor supplies the specific word location.

The random or initial page access is equal to t

ACC

or t

and subsequent page read accesses (as long as the locations specified by

the microprocessor falls within that page) is equivalent to t

PACC

. When CE# is deasserted and reasserted for a subsequent access,

the access time is t

ACC

or t

. Fast page mode accesses are obtained by keeping the read-page addresses constant and changing

the intra-read page addresses.

8.3 Writing Commands / Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the

system must drive WE# and CE# to V

, and OE# to V

The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode,

only two write cycles are required to program a word, instead of four. The Table 18 on page 32 contains details on programming

data to the device using both standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device. Tables 6–9 indicate the address space that each

sector occupies.

Refer to DC Characteristicst on page 77 for the active current specification for the write mode. The AC Characteristics section

contains timing specification tables and timing diagrams for write operations.

8.3.1 Write Buffer

Write Buffer Programming allows the system write to a maximum of 128 words / 256 bytes in one programming operation. This

results in faster effective programming time than the standard programming algorithms.

8.3.2 Accelerated Program Operation

The device offers program operations through the ACC function. This is one of two functions provided by the WP#/ACC or ACC pin,

depending on model number. This function is primarily intended to support manufacturing programming operations at the factory.

If the system asserts V

on this pin, the device automatically enters the Unlock Bypass mode, protected sectors will remain

protected. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V

from the WP#/ACC or ACC pin, depending on model number, returns the device to normal operation. Note that the WP#/ACC or

ACC pin must be raised to V

prior to any accelerated operation and should return to V

after the completion of the

accelerated operation. It should not be at V

for operations other than accelerated programming, or device damage may result.

WP# contains an internal pull-up; when unconnected, WP# is at V

Document Number: 001-98286 Rev. *H Page 16 of 106

S29GL064S

8.3.3 Autoselect Functions

If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read

autoselect codes from the internal register (which is separate from the memory array) on DQ7-DQ0. Standard read cycle timings

ACC

) apply in this mode. Refer to Autoselect Mode on page 19 and Autoselect Command Sequence on page 31 for more

information.

8.4 Automatic ECC

8.4.1 ECC Overview

The Automatic ECC feature works transparently with normal program, erase, and read operations. As the device transfers each

page of data from the Write Buffer to the memory array, internal ECC logic programs the ECC code for that page into a portion of the

memory array that is not visible to the host system. The device evaluates the page data and the ECC code during each initial page

access. If needed, the internal ECC logic will correct a single bit error during the initial access.

Programming more than once to a particular page will disable the ECC function for that page. The ECC function for that page will

remain disabled until the next time the host system erases the sector containing that page. The host system may read data stored in

that page following multiple programming operations; however, ECC remains disables and the device will not detect or correct an

error in that page.

8.4.2 Program and Erase Summary

For performance and reliability reasons, the device performs reading and programming operations on full 32-byte pages in parallel.

Internal device logic provides ECC on each page by adding an ECC code when the page is first programmed.

8.4.3 ECC Implementation

Each 32-byte page in the main flash array, as well as each 32-byte OTP region, features an associated ECC code. Internal ECC

logic is able to detect and correct any single bit error found in a page or the associated ECC code during a read access. The first

Write Buffer program operation applied to a page programs the ECC code for that page. Subsequent programming operations that

occur more than once on a particular page will disable the ECC function for that page. This allows bit or word programming; how-

ever, multiple programming operations to the same page will disable the ECC function on the page where incremental programming

occurs. An erase of the sector containing the page with ECC disabled will re-enable the ECC function for that Page.

The ECC function is automatic and transparent to the user. The transparency of the Automatic ECC function enhances data integrity

for typical programming operations that write data once to each page. The ECC function also facilitates software compatibility to pre-

vious generations of GL Family products by allowing single word programming and bit-walking where the user programs the same

page or word more than once. When a page has Automatic ECC disabled, the ECC function will not detect or correct any errors

upon a data read from that page.

8.4.4 Word Programming

A word programming operation programs a single word anywhere in the main memory array. Programming multiple words within the

same 32-byte page disables the Automatic ECC function for that page. An erase of the sector containing that page will re-enable

Automatic ECC following multiple word programming operation on that page.

8.4.5 Write Buffer Programming

Each Write Buffer program operation allows the user to program a single bit up to 256 bytes. A 32-byte page is the smallest program

granularity that features Automatic ECC protection. Programming to the same page more than once will disable the Automatic ECC

function for that page. Cypress recommends the use of a Write Buffer programming operation to program multiple pages in an oper-

ation and to write each page only once. This keeps the Automatic ECC function enabled on each page. For the very best perfor-

mance, program in full lines of 256 bytes aligned on 256-byte boundaries.

Document Number: 001-98286 Rev. *H Page 17 of 106

S29GL064S

8.5 Standby Mode

When the system is not reading or writing to the device, it can be placed in to standby mode. In this mode, current consumption is

greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V

± 0.3V. (Note that this is a more

restricted voltage range than V

.) If CE# and RESET# are held at V

, but not within V

± 0.3V, the device is in the standby mode,

but the standby current is greater. The device requires standard access time (t

ACC

) for read access when the device is in either

of these standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws active current until the operation is completed.

Refer to the DC Characteristicst on page 77, for the standby current specification.

8.6 Automatic Sleep Mode

The automatic sleep mode reduces device interface energy consumption to the sleep level (I

CC6

) following the completion of a

random read access time. The device automatically enables this mode when addresses remain stable for t

ACC

+ 30 ns. While in

sleep mode, output data is latched and always available to the system. Output of the data depends on the level of the OE# signal

but, the automatic sleep mode current is independent of the OE# signal level. Standard address access timings (t

ACC

or t

PACC

)

provide new data when addresses are changed. Refer to the DC Characteristicst on page 77 for the automatic sleep mode current

specification I

CC6

Automatic sleep helps reduce current consumption especially when the host system clock is slowed for power reduction. During

slow system clock periods, read and write cycles may extend many times their length versus when the system is operating at high

speed. Even though CE# may be Low throughout these extended data transfer cycles, the memory device host interface will go to

the Automatic Sleep current at t

ACC

+ 30 ns. The device will remain at the Automatic Sleep current for t

ASSB

. Then the device will

transition to the standby current level. This keeps the memory at the Automatic Sleep or standby power level for most of the long

duration data transfer cycles, rather than consuming full read power all the time that the memory device is selected by the host

system.

However, the EAC operates independent of the automatic sleep mode of the host interface and will continue to draw current during

an active Embedded Algorithm. Only when both the host interface and EAC are in their standby states is the standby level current

achieved.

8.7 RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for

at least a period of t

, the device immediately terminates any operation in progress, output pins go to High-Z, and all read / write

commands are ignored for the duration of the RESET# pulse. Program / Erase operations that were interrupted should be reinitiated

once the device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at V

±0.3V long enough, the device draws CMOS

standby current (I

CC5

The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the flash memory, enabling the

system to read the boot-up firmware from the flash memory.

Refer to the AC Characteristics on page 84 for RESET# parameters and to Figure 21 on page 83 for the timing diagram.

Document Number: 001-98286 Rev. *H Page 18 of 106

S29GL064S

8.8 Output Disable Mode

When the OE# input is at V

, output from the device is disabled. The output pins are placed in a high impedance state.

8.9 Memory Map

Table 6. S29GL064S (Models 01, 02, V1, V2) Sector Addresses

Sector A21–A15

Sector

Size

(kB/

kwords)

8-bit

Address

Range

16-bit

Address

Range

Sector A21–A15

Sector

Size

(kB/

kwords)

8-bit

Address

Range

16-bit

Address

Range

SA0 0000000 64/32 000000h–00FFFFh 000000h–007FFFh ... ... ... ... ...

SA1 0000001 64/32 010000h–01FFFFh 008000h–00FFFFh SA118 1110110 64/32 760000h–76FFFFh 3B0000h–3B7FFFh

SA2 0000010 64/32 020000h–02FFFFh 010000h–017FFFh SA119 1110111 64/32 770000h–77FFFFh 3B8000h–3BFFFFh

SA3 0000011 64/32 030000h–03FFFFh 018000h–01FFFFh SA120 1111000 64/32 780000h–78FFFFh 3C0000h–3C7FFFh

SA4 0000100 64/32 040000h–04FFFFh 020000h–027FFFh SA121 1111001 64/32 790000h–79FFFFh 3C8000h–3CFFFFh

SA5 0000101 64/32 050000h–05FFFFh 028000h–02FFFFh SA122 1111010 64/32 7A0000h–7AFFFFh 3D0000h–3D7FFFh

SA6 0000110 64/32 060000h–06FFFFh 030000h–037FFFh SA123 1111011 64/32 7B0000h–7BFFFFh 3D8000h–3DFFFFh

SA7 0000111 64/32 070000h–07FFFFh 038000h–03FFFFh SA124 1111100 64/32 7C0000h–7CFFFFh 3E0000h–3E7FFFh

SA8 0001000 64/32 080000h–08FFFFh 040000h–047FFFh SA125 1111101 64/32 7D0000h–7DFFFFh 3E8000h–3EFFFFh

SA9 0001001 64/32 090000h–09FFFFh 048000h–04FFFFh SA126 1111110 64/32 7E0000h–7EFFFFh 3F0000h–3F7FFFh

... ... ... ... ... SA127 1111111 64/32 7F0000h–7FFFFFh 3F8000h–3FFFFFh

Table 7. S29GL064S (Model 03) Top Boot Sector Addresses

Sector A21–A12

Sector

Size

(kB/

kwords)

8-bit

Address

Range

16-bit

Address

Range

Sector A21–A12

Sector

Size

(kB/

kwords)

8-bit

Address

Range

16-bit

Address

Range

SA0 0000000xxx 64/32 000000h–00FFFFh 000000h–007FFFh ... ... ... ... ...

SA1 0000001xxx 64/32 010000h–01FFFFh 008000h–00FFFFh SA125 1111101xxx 64/32 7D0000h–7DFFFFh 3E8000h–3EFFFFh

SA2 0000010xxx 64/32 020000h–02FFFFh 010000h–017FFFh SA126 1111110xxx 64/32 7E0000h–7EFFFFh 3F0000h–3F7FFFh

SA3 0000011xxx 64/32 030000h–03FFFFh 018000h–01FFFFh SA127 1111111000 8/4 7F0000h–7F1FFFh 3F8000h–3F8FFFh

SA4 0000100xxx 64/32 040000h–04FFFFh 020000h–027FFFh SA128 1111111001 8/4 7F2000h–7F3FFFh 3F9000h–3F9FFFh

SA5 0000101xxx 64/32 050000h–05FFFFh 028000h–02FFFFh SA129 1111111010 8/4 7F4000h–7F5FFFh 3FA000h–3FAFFFh

SA6 0000110xxx 64/32 060000h–06FFFFh 030000h–037FFFh SA130 1111111011 8/4 7F6000h–7F7FFFh 3FB000h–3FBFFFh

SA7 0000111xxx 64/32 070000h–07FFFFh 038000h–03FFFFh SA131 1111111100 8/4 7F8000h–7F9FFFh 3FC000h–3FCFFFh

SA8 0001000xxx 64/32 080000h–08FFFFh 040000h–047FFFh SA132 1111111101 8/4 7FA000h–7FBFFFh 3FD000h–3FDFFFh

SA9 0001001xxx 64/32 090000h–09FFFFh 048000h–04FFFFh SA133 1111111110 8/4 7FC000h–7FDFFFh 3FE000h–3FEFFFh

... ... ... ... ... SA134 1111111111 8/4 7FE000h–7FFFFFh 3FF000h–3FFFFFh

Document Number: 001-98286 Rev. *H Page 19 of 106

S29GL064S

8.10 Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes

output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be

programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system

through the command register.

When using programming equipment, the autoselect mode requires V

on address pin A9. Address pins A6, A3, A2, A1, and A0

must be as shown in Table 10 on page 20. In addition, when verifying sector protection, the sector address must appear on the

appropriate highest order address bits (see Table 6–9). Table 10 shows the remaining address bits that are don’t care. When all

necessary bits are set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0. Note

that the A9 pin must not be at V

for operations other than Autoselect, or device damage may result. Autoselect using V

supported at room temperature only. It must be raised to V

prior to any autoselect operations and should return to V

after the

completion of the autoselect operation. It should not be at V

for operations other than autoselect, or device damage may result.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown

in Table 21 on page 42 and Table 23 on page 45. This method does not require V

. Refer to the Autoselect Command Sequence

on page 31 for more information.

Table 8. S29GL064S (Model 04) Bottom Boot Sector Addresses

Sector A21–A12

Sector

Size

(kB/

kwords)

8-bit

Address

Range

16-bit

Address

Range

Sector A21–A12

Sector

Size

(kB/

kwords)

8-bit

Address

Range

16-bit

Address

Range

SA0 0000000000 8/4 000000h–001FFFh 000000h–000FFFh ... ... ... ... ...

SA1 0000000001 8/4 002000h–003FFFh 001000h–001FFFh SA125 1110110xxx 64/32 760000h–76FFFFh 3B0000h–3B7FFFh

SA2 0000000010 8/4 004000h–005FFFh 002000h–002FFFh SA126 1110111xxx 64/32 770000h–77FFFFh 3B8000h–3BFFFFh

SA3 0000000011 8/4 006000h–007FFFh 003000h–003FFFh SA127 1111000xxx 64/32 780000h–78FFFFh 3C0000h–3C7FFFh

SA4 0000000100 8/4 008000h–009FFFh 004000h–004FFFh SA128 1111001xxx 64/32 790000h–79FFFFh 3C8000h–3CFFFFh

SA5 0000000101 8/4 00A000h–00BFFFh 005000h–005FFFh SA129 1111010xxx 64/32 7A0000h–7AFFFFh 3D0000h–3D7FFFh

SA6 0000000110 8/4 00C000h–00DFFFh 006000h–006FFFh SA130 1111011xxx 64/32 7B0000h–7BFFFFh 3D8000h–3DFFFFh

SA7 0000000111 8/4 00E000h–00FFFFh 007000h–007FFFh SA131 1111100xxx 64/32 7C0000h–7CFFFFh 3E0000h–3E7FFFh

SA8 0000001xxx 64/32 010000h–01FFFFh 008000h–00FFFFh SA132 1111101xxx 64/32 7D0000h–7DFFFFh 3E8000h–3EFFFFh

SA9 0000010xxx 64/32 020000h–02FFFFh 010000h–017FFFh SA133 1111110xxx 64/32 7E0000h–7EFFFFh 3F0000h–3F7FFFh

... ... ... ... ... SA134 1111111xxx 64/32 7F0000h–7FFFFFh 3F8000h–3FFFFFh

Table 9. S29GL064S (Models 06, 07, V6, V7) Sector Addresses

Sector A21–A15

Sector

Size

(kB/

kwords)

16-bit

Address

Range

Sector A21–A15

Sector

Size

(kB/

kwords)

16-bit

Address

Range

SA0 0000000 64/32 000000–007FFF ... ... ... ...

SA1 0000001 64/32 008000–00FFFF SA118 1110110 64/32 3B0000–3B7FFF

SA2 0000010 64/32 010000–017FFF SA119 1110111 64/32 3B8000–3BFFFF

SA3 0000011 64/32 018000–01FFFF SA120 1111000 64/32 3C0000–3C7FFF

SA4 0000100 64/32 020000–027FFF SA121 1111001 64/32 3C8000–3CFFFF

SA5 0000101 64/32 028000–02FFFF SA122 1111010 64/32 3D0000–3D7FFF

SA6 0000110 64/32 030000–037FFF SA123 1111011 64/32 3D8000–3DFFFF

SA7 0000111 64/32 038000–03FFFF SA124 1111100 64/32 3E0000–3E7FFF

SA8 0001000 64/32 040000–047FFF SA125 1111101 64/32 3E8000–3EFFFF

SA9 0001001 64/32 048000–04FFFF SA126 1111110 64/32 3F0000–3F7FFF

... ... ... ... SA127 1111111 64/32 3F8000–3FFFFF

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