September 2005 7 M9999-091605
R12 DATA12 I/O External Data Bit.
P12 DATA13 I/O External Data Bit.
U11 DATA14 I/O External Data Bit.
T11 DATA15 I/O External Data Bit.
R11 DATA16 I/O External Data Bit.
P11 DATA17 I/O External Data Bit.
U10 DATA18 I/O External Data Bit.
T10 DATA19 I/O External Data Bit.
U14 DATA2 I/O External Data Bit.
R10 DATA20 I/O External Data Bit.
P10 DATA21 I/O External Data Bit.
U9 DATA22 I/O External Data Bit.
T9 DATA23 I/O External Data Bit.
R9 DATA24 I/O External Data Bit.
P9 DATA25 I/O External Data Bit.
U8 DATA26 I/O External Data Bit.
T8 DATA27 I/O External Data Bit.
R8 DATA28 I/O External Data Bit.
P8 DATA29 I/O External Data Bit.
T14 DATA3 I/O External Data Bit.
R7 DATA30 I/O External Data Bit.
P7 DATA31 I/O External Data Bit.
R14 DATA4 I/O External Data Bit.
P14 DATA5 I/O External Data Bit.
U13 DATA6 I/O External Data Bit.
T13 DATA7 I/O External Data Bit.
R13 DATA8 I/O External Data Bit.
P13 DATA9 I/O External Data Bit.
C11 DEVSELN I/O PCI Device Select Signal. Active Low.
R16 ECSN0 O External I/O Device Chip Select. Active Low.
T16 ECSN1 O External I/O Device Chip Select. Active Low.
U16 ECSN2 O External I/O Device Chip Select. Active Low.
T17 EROEN/ O/I ROM/SRAM/FLASH and External I/O Output Enable. Active Low. WRSTO
WRSTPLS Polarity Select. WRSTPLS = 0, WRSTO = Active High; WRSTPLS = 1, Active
M17 ERWEN0/ O External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.
N17 ERWEN1/ O External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.
P17 ERWEN2/ O External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.
O/I = Output in normal mode; input pin during reset.
R12 DATA12 I/O External Data Bit.
P12 DATA13 I/O External Data Bit.
U11 DATA14 I/O External Data Bit.
T11 DATA15 I/O External Data Bit.
R11 DATA16 I/O External Data Bit.
P11 DATA17 I/O External Data Bit.
U10 DATA18 I/O External Data Bit.
T10 DATA19 I/O External Data Bit.
U14 DATA2 I/O External Data Bit.
R10 DATA20 I/O External Data Bit.
P10 DATA21 I/O External Data Bit.
U9 DATA22 I/O External Data Bit.
T9 DATA23 I/O External Data Bit.
R9 DATA24 I/O External Data Bit.
P9 DATA25 I/O External Data Bit.
U8 DATA26 I/O External Data Bit.
T8 DATA27 I/O External Data Bit.
R8 DATA28 I/O External Data Bit.
P8 DATA29 I/O External Data Bit.
T14 DATA3 I/O External Data Bit.
R7 DATA30 I/O External Data Bit.
P7 DATA31 I/O External Data Bit.
R14 DATA4 I/O External Data Bit.
P14 DATA5 I/O External Data Bit.
U13 DATA6 I/O External Data Bit.
T13 DATA7 I/O External Data Bit.
R13 DATA8 I/O External Data Bit.
P13 DATA9 I/O External Data Bit.
C11 DEVSELN I/O PCI Device Select Signal. Active Low.
R16 ECSN0 O External I/O Device Chip Select. Active Low.
T16 ECSN1 O External I/O Device Chip Select. Active Low.
U16 ECSN2 O External I/O Device Chip Select. Active Low.
T17 EROEN/ O/I ROM/SRAM/FLASH and External I/O Output Enable. Active Low. WRSTO
WRSTPLS Polarity Select. WRSTPLS = 0, WRSTO = Active High; WRSTPLS = 1, Active
M17 ERWEN0/ O External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.
N17 ERWEN1/ O External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.
P17 ERWEN2/ O External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.
R12 DATA12 I/O External Data Bit.
P12 DATA13 I/O External Data Bit.
U11 DATA14 I/O External Data Bit.
T11 DATA15 I/O External Data Bit.
R11 DATA16 I/O External Data Bit.
P11 DATA17 I/O External Data Bit.
U10 DATA18 I/O External Data Bit.
T10 DATA19 I/O External Data Bit.
U14 DATA2 I/O External Data Bit.
R10 DATA20 I/O External Data Bit.
P10 DATA21 I/O External Data Bit.
U9 DATA22 I/O External Data Bit.
T9 DATA23 I/O External Data Bit.
R9 DATA24 I/O External Data Bit.
P9 DATA25 I/O External Data Bit.
U8 DATA26 I/O External Data Bit.
T8 DATA27 I/O External Data Bit.
R8 DATA28 I/O External Data Bit.
P8 DATA29 I/O External Data Bit.
T14 DATA3 I/O External Data Bit.
R7 DATA30 I/O External Data Bit.
P7 DATA31 I/O External Data Bit.
R14 DATA4 I/O External Data Bit.
P14 DATA5 I/O External Data Bit.
U13 DATA6 I/O External Data Bit.
T13 DATA7 I/O External Data Bit.
R13 DATA8 I/O External Data Bit.
P13 DATA9 I/O External Data Bit.
C11 DEVSELN I/O PCI Device Select Signal. Active Low.
R16 ECSN0 O External I/O Device Chip Select. Active Low.
T16 ECSN1 O External I/O Device Chip Select. Active Low.
U16 ECSN2 O External I/O Device Chip Select. Active Low.
T17 EROEN/ O/I ROM/SRAM/FLASH and External I/O Output Enable. Active Low. WRSTO
WRSTPLS Polarity Select. WRSTPLS = 0, WRSTO = Active High; WRSTPLS = 1, Active
M17 ERWEN0/ O External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.
N17 ERWEN1/ O External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.
P17 ERWEN2/ O External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.
R12 DATA12 I/O External Data Bit.
P12 DATA13 I/O External Data Bit.
U11 DATA14 I/O External Data Bit.
T11 DATA15 I/O External Data Bit.
R11 DATA16 I/O External Data Bit.
P11 DATA17 I/O External Data Bit.
U10 DATA18 I/O External Data Bit.
T10 DATA19 I/O External Data Bit.
U14 DATA2 I/O External Data Bit.
R10 DATA20 I/O External Data Bit.
P10 DATA21 I/O External Data Bit.
U9 DATA22 I/O External Data Bit.
T9 DATA23 I/O External Data Bit.
R9 DATA24 I/O External Data Bit.
P9 DATA25 I/O External Data Bit.
U8 DATA26 I/O External Data Bit.
T8 DATA27 I/O External Data Bit.
R8 DATA28 I/O External Data Bit.
P8 DATA29 I/O External Data Bit.
T14 DATA3 I/O External Data Bit.
R7 DATA30 I/O External Data Bit.
P7 DATA31 I/O External Data Bit.
R14 DATA4 I/O External Data Bit.
P14 DATA5 I/O External Data Bit.
U13 DATA6 I/O External Data Bit.
T13 DATA7 I/O External Data Bit.
R13 DATA8 I/O External Data Bit.
P13 DATA9 I/O External Data Bit.
C11 DEVSELN I/O PCI Device Select Signal. Active Low.
R16 ECSN0 O External I/O Device Chip Select. Active Low.
T16 ECSN1 O External I/O Device Chip Select. Active Low.
U16 ECSN2 O External I/O Device Chip Select. Active Low.
T17 EROEN/ O/I ROM/SRAM/FLASH and External I/O Output Enable. Active Low. WRSTO
WRSTPLS Polarity Select. WRSTPLS = 0, WRSTO = Active High; WRSTPLS = 1, Active
M17 ERWEN0/ O External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.
N17 ERWEN1/ O External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.
P17 ERWEN2/ O External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.
R12 DATA12 I/O External Data Bit.
P12 DATA13 I/O External Data Bit.
U11 DATA14 I/O External Data Bit.
T11 DATA15 I/O External Data Bit.
R11 DATA16 I/O External Data Bit.
P11 DATA17 I/O External Data Bit.
U10 DATA18 I/O External Data Bit.
T10 DATA19 I/O External Data Bit.
U14 DATA2 I/O External Data Bit.
R10 DATA20 I/O External Data Bit.
P10 DATA21 I/O External Data Bit.
U9 DATA22 I/O External Data Bit.
T9 DATA23 I/O External Data Bit.
R9 DATA24 I/O External Data Bit.
P9 DATA25 I/O External Data Bit.
U8 DATA26 I/O External Data Bit.
T8 DATA27 I/O External Data Bit.
R8 DATA28 I/O External Data Bit.
P8 DATA29 I/O External Data Bit.
T14 DATA3 I/O External Data Bit.
R7 DATA30 I/O External Data Bit.
P7 DATA31 I/O External Data Bit.
R14 DATA4 I/O External Data Bit.
P14 DATA5 I/O External Data Bit.
U13 DATA6 I/O External Data Bit.
T13 DATA7 I/O External Data Bit.
R13 DATA8 I/O External Data Bit.
P13 DATA9 I/O External Data Bit.
C11 DEVSELN I/O PCI Device Select Signal. Active Low.
R16 ECSN0 O External I/O Device Chip Select. Active Low.
T16 ECSN1 O External I/O Device Chip Select. Active Low.
U16 ECSN2 O External I/O Device Chip Select. Active Low.
T17 EROEN/ O/I ROM/SRAM/FLASH and External I/O Output Enable. Active Low. WRSTO
WRSTPLS Polarity Select. WRSTPLS = 0, WRSTO = Active High; WRSTPLS = 1, Active
M17 ERWEN0/ O External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.
N17 ERWEN1/ O External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.
P17 ERWEN2/ O External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.