ARM系统开发者指南：设计与优化嵌入式系统软件

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"嵌入式ARM基础架构国外经典教程提供了深入理解ARM处理器体系结构和系统设计的宝贵资源，由在行业内有多年经验的专家Andrew N. Sloss和Dominic Symes撰写。本书旨在帮助读者设计和优化运行在ARM处理器上的系统软件。" ARM体系结构是嵌入式计算领域中的一个关键组成部分，它以其低功耗、高性能和广泛的应用范围而著名。Andrew N. Sloss和Dominic Symes的著作详细介绍了这个领域的基础知识，适合那些希望深入理解ARM处理器工作原理的工程师和开发者。关于作者，Andrew N. Sloss拥有丰富的计算机科学背景，自1987年起就与ARM处理器结缘。他在ARM处理器上开发了各种应用，包括为Emerald Publishing设计的首个中文和埃及象形文字编辑系统。他在ARM Inc.工作超过六年，担任技术销售工程师，为开发新产品的企业提供咨询和支持。 Dominic Symes则是英国剑桥ARM Ltd.的软件工程师，自1995年以来一直在从事基于ARM的嵌入式软件开发。他拥有牛津大学的数学学士和博士学位，并且早在1989年就开始编程ARM处理器。本书的内容可能涵盖了以下关键知识点： 1. ARM处理器架构：包括不同系列的ARM处理器（如ARM7, ARM9, Cortex-A, Cortex-M等）的特性，以及它们在指令集、内存管理、中断处理等方面的差异。 2. 指令集架构：深入解析ARM的精简指令集（RISC），包括数据处理、分支、加载/存储等指令，以及Thumb和Thumb-2扩展。 3. 系统设计：介绍如何设计和集成基于ARM的嵌入式系统，包括硬件接口、外设驱动程序、Bootloader的开发，以及与硬件交互的基本原理。 4. 软件优化：讨论如何编写高效代码，包括利用编译器优化选项、理解指令级并行性以及内存访问模式。 5. 实时操作系统（RTOS）：探讨在ARM平台上使用RTOS的概念和实践，如任务调度、中断处理和同步机制。 6. 调试技术：介绍调试工具和方法，如JTAG接口、GDB调试器的使用，以及如何进行性能分析。 7. 电源管理和能耗优化：解释如何在设计中考虑电源效率，包括低功耗模式、动态电压和频率调整（DVFS）。 8. 嵌入式软件开发流程：涵盖从需求分析到系统测试的完整软件开发过程，以及版本控制和文档编制的重要性。通过学习这本书，读者将能够掌握设计高效、可靠的基于ARM的嵌入式系统的技巧，无论是在物联网设备、移动通信还是汽车电子等领域，都能应用这些知识来提升产品的性能和可靠性。

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1.1 The RISC design philosophy

1.2 The ARM Design Philosophy

1.2.1 Instruction Set for Embedded Systems

1.3 Embedded System Hardware

1.3.1 ARM Bus Technology

1.3.2 AMBA Bus Protocol

1.3.3 Memory

1.3.4 Peripherals

1.4 Embedded System Software

1.4.1 Initialization (Boot) Code

1.4.2 Operating System

1.4.3 Applications

1.5

Summary

4 Chapter 1 ARM Embedded Systems

1.1 The RISC design philosophy

The ARM core uses a RISC architecture. RISC is a design philosophy aimed at delivering

simple but powerful instructions that execute within a single cycle at a high clock speed.

The RISC philosophy concentrates on reducing the complexity of instructions performed

by the hardware because it is easier to provide greater ﬂexibility and intelligence in software

rather than hardware. As a result, a RISC design places greater demands on the compiler.

In contrast, the traditional complex instruction set computer (CISC) relies more on the

hardware for instruction functionality, and consequently the CISC instructions are more

complicated. Figure 1.1 illustrates these major differences.

The RISC philosophy is implemented with four major design rules:

1. Instructions—RISC processors have a reduced number of instruction classes. These

classes provide simple operations that can each execute in a single cycle. The compiler

or programmer synthesizes complicated operations (for example, a divide operation)

by combining several simple instructions. Each instruction is a ﬁxed length to allow

the pipeline to fetch future instructions before decoding the current instruction. In

contrast, in CISC processors the instructions are often of variable size and take many

cycles to execute.

2. Pipelines—The processing of instructions is broken down into smaller units that can be

executed in parallel by pipelines. Ideally the pipeline advances by one step on each cycle

for maximum throughput. Instructions can be decoded in one pipeline stage. There is

no need for an instruction to be executed by a miniprogram called microcode as on

CISC processors.

3. Registers—RISC machines have a large general-purpose register set. Any register can

contain either data or an address. Registers act as the fast local memory store for all data

CISC RISC

Compiler

Processor Processor

Code

Generation

Greater

Com

lexit

Greater

Complexity

Code

Generation

Figure 1.1 CISC vs. RISC. CISC emphasizes hardware complexity. RISC emphasizes compiler

complexity.

1.2 The ARM Design Philosophy 5

processing operations. In contrast, CISC processors have dedicated registers for speciﬁc

purposes.

4. Load-store architecture—The processor operates on data held in registers. Separate load

and store instructions transfer data between the register bank and external memory.

Memory accesses are costly, so separating memory accesses from data processing pro-

vides an advantage because you can use data items held in the register bank multiple

times without needing multiple memory accesses. In contrast, with a CISC design the

data processing operations can act on memory directly.

These design rules allow a RISC processor to be simpler, and thus the core can operate

at higher clock frequencies. In contrast, traditional CISC processors are more complex

and operate at lower clock frequencies. Over the course of two decades, however, the

distinction between RISC and CISC has blurred as CISC processors have implemented

more RISC concepts.

1.2 The ARM Design Philosophy

There are a number of physical features that have driven the ARM processor design. First,

portable embedded systems require some form of battery power. The ARM processor has

been speciﬁcally designed to be small to reduce power consumption and extend battery

operation—essential for applications such as mobile phones and personal digital assistants

(PDAs).

High code density is another major requirement since embedded systems have lim-

ited memory due to cost and/or physical size restrictions. High code density is useful for

applications that have limited on-board memory, such as mobile phones and mass storage

devices.

In addition, embedded systems are price sensitive and use slow and low-cost memory

devices. For high-volume applications like digital cameras, every cent has to be accounted

for in the design. The ability to use low-cost memory devices produces substantial savings.

Another important requirement is to reduce the area of the die taken up by the embedded

processor. For a single-chip solution, the smaller the area used by the embedded processor,

the more available space for specialized peripherals. This in turn reduces the cost of the

design and manufacturing since fewer discrete chips are required for the end product.

ARM has incorporated hardware debug technology within the processor so that software

engineers can view what is happening while the processor is executing code. With greater

visibility, software engineers can resolve issues faster, which has a direct effect on the time

to market and reduces overall development costs.

The ARM core is not a pure RISC architecture because of the constraints of its primary

application—the embedded system. In some sense, the strength of the ARM core is that

it does not take the RISC concept too far. In today’s systems the key is not raw processor

speed but total effective system performance and power consumption.

6 Chapter 1 ARM Embedded Systems

1.2.1 Instruction Set for Embedded Systems

The ARM instruction set differs from the pure RISC deﬁnition in several ways that make

the ARM instruction set suitable for embedded applications:

■

Variable cycle execution for certain instructions—Not every ARM instruction executes

in a single cycle. For example, load-store-multiple instructions vary in the number

of execution cycles depending upon the number of registers being transferred. The

transfer can occur on sequential memory addresses, which increases performance since

sequential memory accesses are often faster than random accesses. Code density is also

improved since multiple register transfers are common operations at the start and end

of functions.

■

Inline barrel shifter leading to more complex instructions—The inline barrel shifter is

a hardware component that preprocesses one of the input registers before it is used

by an instruction. This expands the capability of many instructions to improve core

performance and code density. We explain this feature in more detail in Chapters 2, 3,

and 4.

■

Thumb 16-bit instruction set—ARM enhanced the processor core by adding a second

16-bit instruction set called Thumb that permits the ARM core to execute either

16- or 32-bit instructions. The 16-bit instructions improve code density by about

30% over 32-bit ﬁxed-length instructions.

■

Conditional execution—An instruction is only executed when a speciﬁc condition has

been satisﬁed. This feature improves performance and code density by reducing branch

instructions.

■

Enhanced instructions—The enhanced digital signal processor (DSP) instructions were

added to the standard ARM instruction set to support fast 16×16-bit multiplier oper-

ations and saturation. These instructions allow a faster-performing ARM processor in

some cases to replace the traditional combinations of a processor plus a DSP.

These additional features have made the ARM processor one of the most commonly

used 32-bit embedded processor cores. Many of the top semiconductor companies around

the world produce products based around the ARM processor.

1.3 Embedded System Hardware

Embedded systems can control many different devices, from small sensors found on

a production line, to the real-time control systems used on a NASA space probe. All

these devices use a combination of software and hardware components. Each component

is chosen for efﬁciency and, if applicable, is designed for future extension and expansion.

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