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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CPU SIGNAL
DDR3 MEMORY
eMMC, SPI NOR FLASH
SD CARD, SATA
LVDS, HDMI
EPCD EXP PORTS
CAMERA, EXP PORT
SENSORS
AUDIO
USB
EHTERNET
JTAG, DEBUG
mPCIe CONN
AUX SDIO CONN, CAN
GPS MODULE
AUX VOLT REG
Table of Content
TITLE PAGE
CPU POWER
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
Page 9
Page 10
Page 11
Page 12
Page 13
Page 14
Page 15
Page 16
Page 17
Page 18
i.MX6 SMART DEVICE SYSTEM
X1
Revision History
Rev. Code Date Description
11/02/2011 Rev X1 Draft
GENERAL DESIGN NOTES
DC Voltage Output: 5VDC
-
+
AC ADAPTER SPECIFICATIONS
Outer Diameter: 5.5mm
Inner Diameter: 2.1mm
Polarity:
Current Output: ~ 5A (depending on application)
Page 19
Page 20
Page 21
BATTERY CHARGER
PF0100 PMIC
BOOT SELECT
BUILD OPTION TABLES
Page 22
Page 23
PIN MUX TABLEPage 24
COMM CHANNEL STEERING
MCIMX6DL-SDP
A 12/15/2011 Release to Prototype Phase
AX1 02/09/12
Draft Rev B Respin:
- Changed Audio CODEC to WM8962 per Marketing Request.
- Removed two digital microphones. Changed mics to Wolfson WM2730 per Marketing.
- Connected NVCC_JTAG rail to GEN_3V3.
- Added PFET Switch to SWBST supply to isolate it from System power.
- Changed HDMI Media guard to CM2020 IC to correct I2C HDMI issue.
- Changed voltage sides on U9 level shifter.
- Changed SW4 to 3.15V output. Moved audio 1.8V to GEN_1V8.
- Changed camera 1V5 supply to VGEN2, other 1V5 loads moved to VGEN1.
- Added isolation PFETs to Audio voltage supplies.
- Switched USB_OTG_ID to pin ENET_RX_ER, USBOTG_OC to pin EIM2
and USBH1_OC to pin EIM_D30 to match pinmux functionality.
- Added parallel termination resistors to PCIe differential clock traces.
- Added next generation DEVSLP option for SATA connection.
- Moved DISP0_PWR_EN to NANDF_WP_B to correct pull up voltage issue.
- Deleted auxiliary 3.15V voltage regulator.
- Designated several capacitors on processor core power rails as DNP.
Validation proved unnecessary.
- Moved I2C3 SDA from GPIO_16. This pin must be unconnected for
Ethernet 1588 (time stamp) functionality to work.
- Added shield ground pins to LVDS connectors.
- Changed extrnal speaker capacitors to higher voltage rating.
- Changed external regulator to supply 3.0V power to VSNVS.
- Changed PF0100 microprocessor program circuit to DNP.
- Added 5V supply to LCD expansion headers.
- Connected HPOUTFB directly to Audio GND.
- Connected VDDOTP to ground to boot PMIC from program settings.
- Added isolation to prevent back powering board from USB when no battery present.
- Back annotated Schematic to Layout. REFDES may have changed from Rev A.
- Populated optional "PWRON" button circuit for use with Android.
- Removed write protect on NOR Flash.
- Removed LC filter circuit from external speakers.
- Added an additional 2 100uF capacitors to MPCIE_3V3 next to connector.
- Updated Power Rail, IOMUX, and Configuration Tables.
B 02/17/12 Release to Production
B1 04/11/12
Release to Production
- Depopulated Q512 because of schematic error.
- Cut trace to U12 pin 5 to prevent false USB plug in detects.
- Added schematic page to detail applicable board TDAs that affect Rev B boards.
- Populating CAN components U517 and U518 per Marketing Request.
- Added resistor RX1 across pads for C55 to improve 24MHz clock stability.
- Pull up resistors R629 and R639 have been changed to DNP.
- R30 is DNP to support TO1.0 issue on i.MX6 DualLite Silicon.
TEMPORARY DEVIATIONSPage 25
- Changed Marketing part number to MCIMX6DL-SDP
- Changed R7, R112 and R585 to DNP
- Changed C540 to "POPULATED"
- Added notes that the SATA interface does not exist on the i.MX6 DualLite
version of the i.MX6 Processor Familiy.
B2 05/04/12
B3 05/25/12
- Changed DDR3 Memory to new 1.35V capable memory MT41K128M16JT.
- Changed C540 to 1.0 uF per Wolfson recommendation.
- Changed R183 and R189 to 2.37K pull ups to bring I2C rise time into specification.
B4 07/18/12
- Removed buffers U500 and U520 from digital microphone data outputs.
A note is added to show required hand wire modification.
- The Battery Charge Done LED is disconnected and R522 is depopulated.
New parts RX2, CX1 and UX1 are added. Traces show required hand modifications.
- Optional Power On Circuit has been disabled and U511 and R578
are now DNP. A new Diode DX1 has been added to allow EIM_D29
to sense a button press.
- RESET button SW2 now connects to the PWRON pin of the PMIC.
- Added 10K pull down resistor RX3 to SDCKE0 trace.
- SIM Card Connector CON1 is now populated by default.
- Battery Connector Header CON3 is now populated by default.
- Changed resistors R174 and R176 and to depopulated by default.
LVDS0 EDID will not be connected to I2C2 channel unless needed.
1. Unless Otherwise Specified:
All resistors are in ohms, 5%, 1/16 Watt
All capacitors are in uF, 20%, 50V
All voltages are DC
All polarized capacitors are Tantalum
3. Interrupted lines coded with the same letter or letter
combinations are electrically connected.
4. Device type number is for reference only. The number
varies with the manufacturer.
5. Special signal usage:
_B or 'n' Denotes - Active-Low Signal
<> or [] Denotes - Vectored Signals
6. Interpret diagram in accordance with American
National Standards Institute specifications, current
revision, with the exception of logic block symbology.
2. Critical compenents that require tolerances tighter
than listed in Note 1are labeled with required tolerance
on schematic. Non-critical components may be filled
with tighter tolerance parts for BOM consolidation
purposes, but may be changed to meet the general
tolerances of Note 1 if desired.
- Changed U1 to i.MX 6 TO1.2 processor.
- Changed C68 and C612 to DNP.
- Populated C682 and C716 with 22uF capacitors.
09/25/12B5
- All hand wire changes made in Revision B4 are now formally made in the netlist
and the layout files.
- Q512 is changed to populated.
- Optional Start Up circuit has been modified.
- PMIC Programming Micro-Processor is removed.
- CX1 capacitor is changed to C504
- DX1 diode is changed to D4
- RX1 resistor changed to R216
- RX2 resistor changed to R19
- RX3 resistor changed to R635
- UX1 buffer changed to U507
- Add DNP Input to U13 buffer for USB_OTG_PWR_EN.
Buffer now powered from GEN_3V3.
- FA_ANA and VDD_FA signals now connected to ground.
- Added resistor options to EIM_DA7 trace to EPD connector.
- Connected EIM_DA9 to EPDC connector J508 to supply SDCE5 if needed.
- Optional LDO U9 is now depopulated.
- Added Connector J13 to support BT from SDIO Card through DNP resistors.
- Added GPIO control of Battery Charge Enable pins through DNP resistor.
- Changed C594 to 0.22uF
- Changed C31 to 47uF.
- Added C555 as second 22uF capacitor in parallel with C546.
- Changed C561, C562, C586 and C596 to 0.47uF.
- Added additional 47uF bulk capacitor C769 to SD2 socket VDD supply.
- Added option to route HDMI DDC comms seperate from I2C2 comms channel.
- C597 populated to provide de-bounce to RESET circuit.
- Depopulated C68, C612. Populated C682, C716 closer to pins.
- Depopulated C39, C606, C607, C608, C609, C610, C673 and C681.
- Added DNP R302 to provide alternate 5V supply path to USB_H1_VBUS.
- Added DNP R632 to provide alternate gating of PMIC_5V source (tied to VDDSOC).
- Added DNP L25 and L26 to provide alternate 2.8V supply path to camera modules.
- Added test pads to LVDS third data lanes to support testing with will 24-bit panels.
- Changed capacitors C6 and C7 to Zero Ohm resistors.
- Changed Battery Charge ICs U502 and U503 to MAX8903C version.
10/01/12C1
C2 11/09/12
X
- Moved Ferrite Beads L10 and L17 to pads for L15 and L26.
Camera Analog Voltage supply moved to VGEN3.
- Added notes for 24MHz crystal and USB layout design.
- Changed R17, R21, R25, R27, R68, R85, R582, and R660 to 1% resistors
due to lead time availability issues.
Drawing Title:
Size
Document Number
Rev
Date:
Sheet
of
Page Title:
Designer:
Drawn by:
Approved:
Multimedia Application Division,
Wireless & Mobile System Group
This document contains information proprietary to Freescale Semiconductor and shall not be used for
engineering design, procurement or manufacture in whole or in part without the express written permission
of Freescale Semiconductor.
ICAP Classification: FCP: _____ FIUO: _____ PUBI: _____
SOURCE:SCH-27417 PDF:SPF-27417 C2
MCIMX6DL-SMART DEVICE PLATFORM
D
Friday, November 09, 2012
TITLE PAGE
Mark Middleton
<Approver>
Mark Middleton
125
Drawing Title:
Size
Document Number
Rev
Date:
Sheet
of
Page Title:
Designer:
Drawn by:
Approved:
Multimedia Application Division,
Wireless & Mobile System Group
This document contains information proprietary to Freescale Semiconductor and shall not be used for
engineering design, procurement or manufacture in whole or in part without the express written permission
of Freescale Semiconductor.
ICAP Classification: FCP: _____ FIUO: _____ PUBI: _____
SOURCE:SCH-27417 PDF:SPF-27417 C2
MCIMX6DL-SMART DEVICE PLATFORM
D
Friday, November 09, 2012
TITLE PAGE
Mark Middleton
<Approver>
Mark Middleton
125
Drawing Title:
Size
Document Number
Rev
Date:
Sheet
of
Page Title:
Designer:
Drawn by:
Approved:
Multimedia Application Division,
Wireless & Mobile System Group
This document contains information proprietary to Freescale Semiconductor and shall not be used for
engineering design, procurement or manufacture in whole or in part without the express written permission
of Freescale Semiconductor.
ICAP Classification: FCP: _____ FIUO: _____ PUBI: _____
SOURCE:SCH-27417 PDF:SPF-27417 C2
MCIMX6DL-SMART DEVICE PLATFORM
D
Friday, November 09, 2012
TITLE PAGE
Mark Middleton
<Approver>
Mark Middleton
125
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
-->
-->
MX6 power domains
under-BGA decoupling
(These capacitors are part of i.MX6 DDR3
Power Domain. They decouple pins shown
on Page 4 of these schematics)
NOTE:
Freescale has validated two difference sets of decoupling capacitors and board layouts
for use with the i.MX 6 processor. The customer is free to choose the desired decoupling
scheme. This scheme uses fewer components. The alternate scheme can be found
on the ARD board. Refer to SCH-27142 and LAY-27142.
Extra Bulk Capacitors
NOTE:
In early designs of the Smart Device board, these bulk capacitors were used.
After testing of the board, it was found that these capacitors could be
removed with no effect. This reduces the capacitve loading on the internal processor
LDOs. The coponents/footprints have been left in place in the event that future
applications and/or software changes show that these capacitors are needed.
NOTE:
The VDDARM_CAP and VDDARM23_CAP rails have been optimized for use with the i.MX 6 Quad and i.MX 6 DualLite processors.
To achieve the lowest power mode (preventing internal leakage) when using the i.MX 6 Dual and the i.MX 6 SoloLite
processors, VDDARM_CAP should be split from VDDARM23_CAP and the VDDARM23_CAP pins should be connected to ground.
This can be done on a single board configured for use with all four processors by placing a Zero Ohm resistor between the
VDDARM_CAP and VDDARM23_CAP rails (in place of the straight net connection). To use the board with different processors,
populate the resistor when using Quad and DualLite processors and depopulate resistor when using Dual and SoloLite
processors. When using Dual and SoloLite processors, depopulate the capacitors attached to VDDARM23_CAP pins and
replace one of the capacitors with a zero Ohm resistor to short pins to ground. The configuration in this schematic will work with
all four processors, but will not result in the most power optimized configuration for the i.MX 6 Dual and Solo processors.
LAYOUT NOTE:
It is critical that the bulk and decoupling capacitors placed on the VDDARM_CAP, VDDARM23_CAP, VDDSOC_CAP
and VDDPU rails be placed directly underneath the processors. Development testing has shown that proper
placement of the capacitors can reduce ripple on the voltage rails by as much as 50% compared to placing
capacitors outside the physical boundaries of the processor. These will result in more stable processor operations.
NOTE:
Diode D10 is required to correct a problem on a small number of i.MX6 DualLite parts in which VDDSNVS does
not come up when VDDHIGH_IN is applied. A similar problem was corrected on i.MX6Q TO1.2 processors. The
diode is left populated for similarity across the Smart Device family of boards.
NVCC_SD1
NVCC_SD1
NVCC_MIPI
NVCC_CSI
NVCC_MIPI
NVCC_EIM
NVCC_EIM
NVCC_EIM
NVCC_EIM
NVCC_CSI
GND GND
GNDGND
VDDSOC_VPVDDSOC_CAP
VDD_SNVS_CAP
VDDCORE
VGEN5_2V8
NVCC_PLL_OUT
VSNVS_3V0
GND
VDDPU
VDDHIGH_VPH
GND
GND
VDDSOC
GND
GEN_1V8
GND
NVCC_RGMII
GEN_2V5
VDDHIGH_IN
GND
GND
GND
GND
GEN_1V8
GND
GND
GND
VDDSOC_CAP
GND
GND
GND
GND
GND
GND
VDDHIGH_VPH
GND
GND
GND
NVCC_3V3
GEN_3V3
GEN_3V3
VGEN3_2V5
GND
GND
DDR_1V5
NVCC_3V3
NVCC_3V3
NVCC_3V3
GEN_2V5
ETH_3V3
VDD_ARM_CAP
VDD_SNVS_CAP
GND GND GND
VDDSOC_CAP VDDPU
GND
Drawing Title:
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Document Number
Rev
Date:
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ICAP Classification:
FCP:
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PUBI:
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D
Friday, November 09, 2012
CPU POWER
225
X___
Drawing Title:
Size
Document Number
Rev
Date:
Sheet
of
Page Title:
ICAP Classification:
FCP:
FIUO:
PUBI:
SOURCE:SCH-27417 PDF:SPF-27417 C2
MCIMX6DL-SMART DEVICE PLATFORM
D
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CPU POWER
225
X___
Drawing Title:
Size
Document Number
Rev
Date:
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ICAP Classification:
FCP:
FIUO:
PUBI:
SOURCE:SCH-27417 PDF:SPF-27417 C2
MCIMX6DL-SMART DEVICE PLATFORM
D
Friday, November 09, 2012
CPU POWER
225
X___
C688
0.22UF
6.3V
C691
0.22UF
6.3V
i.MX6U - POWER
U1E
PCIMX6U8DVM10AB
GND_1
A13
GND_2
A25
GND_3
A4
GND_4
A8
GND_5
AA10
GND_6
AA13
GND_7
AA16
GND_8
AA19
GND_9
AA22
GND_10
AA7
GND_11
AB24
GND_12
AB3
GND_13
AD10
GND_14
AD13
GND_15
AD16
GND_16
AD19
GND_17
AD22
GND_18
AD4
GND_19
AD7
GND_20
AE1
VDDARM_CAP_1
H13
VDDARM_CAP_2
J13
VDDARM_CAP_3
K13
VDDARM_CAP_4
L13
VDDARM_CAP_5
M13
VDDARM_IN_1
H14
VDDARM_IN_2
J14
VDDARM_IN_3
K14
VDDARM_IN_4
L14
VDDARM_IN_5
M14
VDDARM_IN_6
N14
VDDARM_IN_7
P14
NVCC_LCD
P19
NVCC_NANDF
G15
NVCC_PLL_OUT
E8
NVCC_RGMII
G18
NVCC_SD3
G14
VDDSOC_CAP_1
R10
VDDSOC_CAP_2
T10
VDDSOC_IN_6
N16
VDD_FA
B5
VDDPU_CAP_9
J17
VDDPU_CAP_10
K17
VDDPU_CAP_11
L17
VDDSOC_IN_4
L16
VDDSOC_IN_3
K16
VDDSOC_IN_2
J16
NVCC_EIM0
K19
VDDSOC_CAP_3
T13
GPANAIO
C8
GND_21
AE25
GND_22
B4
GND_23
C1
GND_24
C10
GND_25
C4
GND_26
C6
NVCC_JTAG
J7
GND_27
D3
GND_28
D6
GND_29
D8
VDDARM_CAP_6
N13
VDDARM_CAP_7
P13
VDDARM_CAP_8
R13
VDDARM_CAP_9
H11
VDDARM_CAP_10
J11
VDDARM_CAP_11
K11
VDDARM_CAP_12
L11
VDDARM_IN_8
R14
VDDSOC_IN_7
P16
VDDSOC_CAP_4
T14
VDDSOC_IN_8
R16
NVCC_EIM1
L19
NVCC_ENET
R19
VDDPU_CAP_8
H17
NVCC_SD2
G17
VDDARM_CAP_16
R11
VDDARM_CAP_13
M11
VDDARM_CAP_14
N11
NVCC_GPIO
P7
VDDARM_CAP_15
P11
NVCC_SD1
G16
GND_30
E5
GND_31
E6
GND_32
E7
GND_33
F5
GND_34
F6
GND_35
F7
GND_36
F8
GND_37
G10
GND_38
G19
GND_39
G3
GND_40
H12
GND_41
H15
GND_42
H18
GND_43
H8
GND_44
J12
GND_45
J15
GND_46
J18
GND_47
J2
GND_48
J8
GND_49
K10
GND_50
K12
VDDHIGH_CAP_1
H10
VDDHIGH_CAP_2
J10
VDD_SNVS_CAP
G9
VDDHIGH_IN_2
J9
VDDHIGH_IN_1
H9
VDD_SNVS_IN
G11
NVCC_CSI
N7
NVCC_EIM2
M19
VDDSOC_IN_5
M16
VDDSOC_IN_1
H16
VDDSOC_IN_9
T16
VDDSOC_IN_10
U16
VDDPU_CAP_12
M17
VDDSOC_CAP_5
U10
GND_51
K15
GND_52
K18
GND_53
K8
GND_54
L10
GND_55
L12
GND_56
L15
GND_57
L18
GND_58
L2
GND_59
L5
GND_74
P8
GND_75
R12
GND_76
R15
GND_77
R17
GND_78
R8
GND_79
T11
GND_60
L8
GND_61
M10
GND_62
M12
GND_63
M15
GND_64
M18
GND_65
M8
GND_66
N10
GND_67
N15
GND_68
N18
GND_72
P15
GND_73
P18
GND_71
P12
GND_70
P10
GND_69
N8
NVCC_MIPI
K7
GND_80
T12
GND_81
T15
GND_82
T17
GND_83
T19
GND_84
T8
GND_85
U11
GND_86
U12
GND_87
U15
GND_88
U17
VDDARM_IN_9
K9
VDDARM_IN_10
L9
VDDARM_IN_11
M9
VDDARM_IN_12
N9
VDDARM_IN_13
P9
VDDARM_IN_14
R9
VDDARM_IN_15
T9
VDDARM_IN_16
U9
VDDPU_CAP_13
N17
VDDPU_CAP_14
P17
VDDSOC_CAP_6
U13
VDDSOC_CAP_7
U14
FA_ANA
A5
GND_89
U8
GND_90
U19
GND_91
V8
GND_92
V19
GND_93
W3
GND_94
W7
GND_95
W8
GND_96
W9
GND_97
W10
GND_98
W11
GND_99
W12
GND_100
W13
GND_101
W15
GND_102
W16
GND_103
W17
GND_104
W18
GND_105
W19
GND_106
Y5
GND_107
Y24
C698
0.22UF
6.3V
R47 0
C686
0.22UF
6.3V
C705
0.22UF
6.3V
C659
0.22UF
6.3V
C662
0.22UF
6.3V
C663
0.22UF
6.3V
C646
0.22UF
6.3V
C687
0.22UF
6.3V
C719
0.22UF
6.3V
C645
0.22UF
6.3V
C674
0.22UF
6.3V
C643
0.22UF
6.3V
C650
0.22UF
6.3V
R45 0
SH503
SOLDER SHORT
C712
0.22UF
6.3V
C730
22UF
6.3V
C716
22UF
4V
C644
0.22UF
6.3V
C680
22UF
4V
C661
0.22UF
6.3V
C664
0.22UF
6.3V
SH17
SOLDER SHORT
C605
22UF
6.3V
C637
0.22UF
6.3V
C634
0.22UF
6.3V
C649
22UF
4V
C68
22UF
DNP
C684
0.22UF
6.3V
C677
0.22UF
6.3V
C721
0.22UF
6.3V
C693
0.22UF
6.3V
C714
0.22UF
6.3V
C636
0.22UF
6.3V
C672
0.22UF
6.3V
C690
0.22UF
6.3V
C682
22UF
4V
R625 0
C40
22UF
4V
C655
0.01UF
6.3V
C710
0.22UF
6.3V
C685
0.22UF
6.3V
C69
22UF
6.3V
C704
0.22UF
6.3V
C648
0.22UF
6.3V
C623
22UF
6.3V
C656
0.22UF
6.3V
C724
0.22UF
6.3V
C676
0.22UF
6.3V
C708
0.22UF
6.3V
R104 0
C658
0.22UF
6.3V
C657
0.22UF
6.3V
C725
0.22UF
6.3V
C629
0.22UF
6.3V
C723
0.22UF
6.3V
C669
22UF
4V
C630
0.22UF
6.3V
C665
0.22UF
6.3V
C660
0.22UF
6.3V
C703
0.22UF
6.3V
C696
0.22UF
6.3V
D10
NSR0320
A C
C695
0.22UF
6.3V
C715
0.22UF
6.3V
C654
22UF
6.3V
C701
0.22UF
6.3V
C38
22UF
4V
C612
22UF
DNP
C720
0.22UF
6.3V
C709
0.22UF
6.3V
C628
0.22UF
6.3V
R85 0.02
DNP
1%
C671
0.22UF
6.3V
C683
22UF
4V
C611
22UF
DNP
C675
0.22UF
6.3V
C729
22UF
6.3V
C54
DNP
C670
0.22UF
6.3V
C604
22UF
4V
C679
22UF
4V
C706
0.22UF
6.3V
C722
0.22UF
6.3V
C713
0.22UF
6.3V
C707
0.22UF
6.3V
C711
0.22UF
6.3V
R727 0
C702
0.22UF
6.3V
C692
0.22UF
6.3V
C652
0.22UF
6.3V
C694
22UF
4V
C689
0.22UF
6.3V
SH16
SOLDER SHORT
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Layout: High speed data lines : 50 ohms
CSI_MCLK
HSYNC
CNTRST
VSYNC
DRDY
Depopulate R121, R123, R133, R138, R139,
R167, R168, and R627 when using E-BOOK
Card in 16-bit Data Mode.
Refer to build options table for assembly
options on muxed signal resistors.
Place C726
close to i.MX6.
Note: The SATA interface on the i.MX6 DualLite Processor
is disabled. These pins have been diabled. This block has
been left in only to provide continuity with other Smart Devices
that use the same PCB,
{NVCC_CACHE POWER}
SECURE HDMI COMMUNICATIONS
NOTE:
To configure SD board to run in Secure HDMI mode:
1) Depopulate R153 and R154 (schematic page 22)
This removes HDMI comms channel from I2C2.
2) Populated R218 and R219.
This connects HDMI comms to DDC capable pins.
3) Depopulate R168.
This deconflicts HDMI comms from the compass interrupt.
4) Populate R217 to connect COMP_INT to processor.
This connects COMP_INT to a different GPIO pin.
5) R167 may be left populated or depopulated as desired.
Extra Bulk Capacitors
NOTE:
In early designs of the Smart Device board, these bulk capacitors were used.
After testing of the board, it was found that these capacitors could be
removed with no effect. This reduces the capacitve loading on the internal processor
LDOs. The coponents/footprints have been left in place in the event that future
applications and/or software changes show that these capacitors are needed.
Note:
1) R216 is required to correct
a known 24MHz slow starting
issue present on some iMX 6
part. Please refer to the i.MX 6
Processor Errata, issue
# ERR003745 for more details.
2) Per bulletin EB830, the i.MX6
processor may drive the 24 MHz
crystal up to 250 uW. Freescale
recommends following the guidelines
contained in the bulletin.
The HW Developer Guide contains
additional information.
HDMI_VP
HDMI_RESREF
EIM_D26
KEY_ROW2
EIM_D21
EIM_D22
EIM_DA0
EIM_D18
HDMI_DDCCEC
SD3_RST
PCIE_VPTX
PCIE_VP
PCIe_REXT
EIM_EB3
EIM_D24
EIM_D25
EIM_D25
EIM_EB0
EIM_D30
EIM_D21
EIM_D22
DSI_REXT
DSP0_DAT9
DSP0_DAT8
DSP0_DAT22
DSP0_DAT6
DSP0_DAT20
DSP0_DAT4
DSP0_DAT17
DSP0_DAT1
DSP0_DAT16
DSP0_DAT0
DSP0_DAT15
DSP0_DAT14
DSP0_DAT11
DSP0_DAT10
DSP0_DAT7
DSP0_DAT23
DSP0_DAT5
DSP0_DAT21
DSP0_DAT3
DSP0_DAT19
DSP0_DAT2
DSP0_DAT18
DSP0_DAT13
DSP0_DAT12
DSP0_CLK
DI0_PIN4
DI0_PIN3
DI0_PIN15
DI0_PIN2
LVDS_2V5
RTC_XTALO
RTC_XTALI
CPU_XTALI
CPU_XTALO
PCIE_VPH
HDMI_VPH
VDDUSB
EIM_WAIT
EIM_BCLK
EIM_D24
EIM_D23
EIM_DA13
EIM_DA14
EIM_A25
EIM_D28
EIM_DA8
EIM_DA15
KEY_COL4
EIM_D16
KEY_COL7
KEY_ROW7
SPDIF_CLK
DISP0_SER_RS
SPDIF_OUT
KEY_COL5
EIM_DA9
DISP0_PWM
DISP0_PWM
ENET_REFCLK
KEY_ROW5
KEY_ROW6
EIM_CS1
KEY_COL6
KEY_ROW4
HDMI_CEC_IN
EIM_D19
CSI_REXT
SATA_VP
SATA_VPH
SATA_REXT
TP32_16767721
TP31_16767721
TP510
TP509
EIM_DA15
EIM_D16
EIM_EB2
SATA_VP SATA_VPH HDMI_VP HDMI_VPH PCIE_VP PCIE_VPTX PCIE_VPHLVDS_2V5
LDO_USB_IN
VDDSOC_VP
GND GND
VDDSOC_VP
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GEN_2V5
GEN_2V5
GEN_2V5
GEN_1V8GEN_3V3
GND GND
GND
GND
GND
USB_OTG_VBUS
ETH_3V3
VDDSOC_VP
GEN_2V5
GND
GND
GND
GND
VDDSOC_CAP
GNDGNDGND GND GND GND GND GND
GND
USB_H1_VBUS
PMIC_5V
SD2_DATA0
15
SD2_DATA1
15
SD2_DATA2
15
SD2_DATA3
15
SD2_CLK
15
SD2_CMD
15
SD3_DATA0
6
SD3_DATA1
6
SD3_DATA2
6
SD3_DATA3
6
SD3_DATA4
6
SD3_DATA5
6
SD3_DATA6
6
SD3_DATA7
6
SD4_DATA0
5
SD4_DATA1
5
SD4_DATA2
5
SD4_DATA3
5
SD4_DATA4
5
SD4_DATA5
5
SD4_DATA6
5
SD4_DATA7
5
SD2_DATA4
15
SD2_DATA5
15
SD2_DATA6
15
SD2_DATA7
15
SD2_CD_B
15
SD2_WP
15
SD3_CD_B
6
SD3_WP
6
SD4_CMD
5
SD4_CLK
5
CABC_EN0
7
CAP_TCH_INT0
7
I2C3_SDA
22
I2C3_SCL
22
I2C2_SCL
22
I2C2_SDA
22
HDMI_CEC_IN
7
SD3_CMD
6
SD3_CLK
6
HDMI_CLKM
7
HDMI_CLKP
7
HDMI_D0M
7
HDMI_D0P
7
HDMI_D1M
7
HDMI_D1P
7
HDMI_D2M
7
HDMI_D2P
7
HDMI_HPD
7
LVDS0_TX0_N
7
LVDS0_TX0_P
7
LVDS0_TX1_N
7
LVDS0_TX1_P
7
LVDS0_TX2_N
7
LVDS0_TX2_P
7
LVDS0_CLK_N
7
LVDS0_CLK_P
7
LVDS1_TX0_N
7
LVDS1_TX0_P
7
LVDS1_TX1_N
7
LVDS1_TX1_P
7
LVDS1_TX2_N
7
LVDS1_TX2_P
7
LVDS1_CLK_N
7
LVDS1_CLK_P
7
CABC_EN1
7
CAP_TCH_INT1
7
CSI0_PWN
8,9
CSI0_RST_B
8,9
UART1_TX
13
I2C1_SCL
22
I2C1_SDA
22
CSI0_DAT12
8,9
CSI0_DAT13
8,9
CSI0_DAT14
8,9
CSI0_DAT15
8,9
CSI0_DAT16
8,9
CSI0_DAT17
8,9
CSI0_DAT18
8,9
CSI0_DAT19
8,9
CSI0_HSYNCH
8,9
CSI0_VSYNCH
8,9
CSI0_PIXCLK
8,9
DISP_RST_B
8
DISP_PWR_EN
8
CSI_CLK0M
8
CSI_CLK0P
8
CSI_D0M
8
CSI_D0P
8
CSI_D1M
8
CSI_D1P
8
DSI_CLK0M
8
DSI_CLK0P
8
DSI_D0M
8
DSI_D0P
8
DSI_D1M
8
DSI_D1P
8
DISP0_DAT0
9
DISP0_DAT1
9
DISP0_DAT2
9
DISP0_DAT3
9
DISP0_DAT4
9
DISP0_DAT5
9
DISP0_DAT6
9
DISP0_DAT7
9
DISP0_DAT8
9
DISP0_DAT9
9
DISP0_DAT10
9
DISP0_DAT11
9
DISP0_DAT12
9
DISP0_DAT13
9
DISP0_DAT14
9
DISP0_DAT15
9
DISP0_DAT16
9
DISP0_DAT17
9
DISP0_DAT18
9
DISP0_DAT19
9
DISP0_DAT20
9
DISP0_DAT21
9
DISP0_DAT22
9
DISP0_DAT23
9
DISP0_HSYNCH
9
DISP0_VSYNCH
9
DISP0_CNTRST
9
DISP0_DRDY
9
DISP0_CLK
9
CODEC_PWR_EN
10
AUD3_RXD
10
AUD3_TXFS
10
AUD3_TXD
10
AUD3_TXC
10
HEADPHONE_DET
10
USB_OTG_DN
11
USB_OTG_DP
11
USB_OTG_PWR_EN
11
USB_OTG_OC
11
RGMII_TXCLK
12
RGMII_RXCLK
12
RGMII_TXD0
12
RGMII_TXD1
12
RGMII_TXD2
12
RGMII_TXD3
12
RGMII_TXEN
12
RGMII_RXD0
12
RGMII_RXD1
12
RGMII_RXD2
12
RGMII_RXD3
12
RGMII_RXDV
12
RGMII_MDIO
12
RGMII_MDC
12
ENET_REF_CLK
12
RGMII_INT
12
RGMII_nRST
12
JTAG_TDO
13
JTAG_MOD
13
JTAG_TCK
13
JTAG_TMS
13
JTAG_TDI
13
JTAG_nTRST
13
UART1_RX
13
ACCL_INT_IN
14
ALS_INT
14
BARO_INT
14
COMP_INT
14
SENSOR_PWR_EN
14
CLK1_N
16
CLK1_P
16
PCIE_TXM
16
PCIE_RXM
16
PCIE_TXP
16
PCIE_RXP
16
USB_HOST_DN
16
USB_HOST_DP
16
PCIE_PWR_EN
16
GPIO_0_CLKO
8,9
USB_OTG_ID
11
GPS_PWREN
17
GPS_PPS
17
UART3_TXD
17
UART3_RXD
17
GPS_RESET_B
17
CHG_STATUS1_B
18
CHG_FLT1_B
18
CHG_STATUS2_B
18
CHG_FLT2_B
18
PMIC_ON_REQ
19
PMIC_STBY_REQ
19
PMIC_INT_B
19
PCIE_DIS_B
16
PCIE_RST_B
16
KEY_VOL_UP
21
KEY_VOL_DN
21
USR_DEF_RED_LED
21
BOOT_MODE0
21
BOOT_MODE1
21
TEST_MODE
21
TAMPER
21
EIM_A16
9,21
EIM_A17
9,21
EIM_A18
9,21
EIM_A19
9,21
EIM_A20
9,21
EIM_A21
9,21
EIM_A22
9,21
EIM_A23
9,21
EIM_A24
9,21
EIM_DA0
9,21
EIM_DA1
9,21
EIM_DA2
9,21
EIM_DA3
9,21
EIM_DA4
9,21
EIM_DA5
9,21
EIM_DA6
9,21
EIM_DA7
9,21
EIM_DA8
9,21
EIM_DA10
9,21
EIM_DA11
9,21
EIM_DA12
9,21
EIM_DA13
9,21
EIM_DA14
9,21
EIM_DA15
9,21
EIM_WAIT
21
EIM_LBA
9,21
EIM_EB0
9,21
EIM_EB1
9,21
EIM_RW
9,21
EIM_EB2
9,21
EIM_EB3
21
EIM_A25
9
EIM_D16
9
EIM_D17
9
EIM_D18
9
EIM_D19
9
EIM_D20
9
EIM_D23
9
EIM_D26
9
EIM_D27
9
EIM_D28
9
EIM_D30
9
EIM_D31
9
EIM_BCLK
9
CSPI1_MISO
22
CSPI1_CLK
22
CSPI1_MOSI
22
CSPI1_CS0
22
TS_INT
9
EIM_OE
9
EIM_CS0
9
CAN1_TX
15
CAN1_RX
15
CAN1_STBY
15
USB_H1_PWR_EN
11
USB_H1_OC
11
EIM_CS1
9
DI0_D0_CS
9
DI0_D1_CS
9
DISP0_RD
9
DISP0_PWR_EN
9
DISP0_RST_B
9
KEY_COL4
9
KEY_ROW4
9
KEY_COL5
9
KEY_ROW5
9
KEY_COL6
9
KEY_ROW6
9
KEY_COL7
9
KEY_ROW7
9
SPDIF_CLK
9
SPDIF_OUT
9
DISP0_SER_RS
9
EIM_DA9
21
CSI_PWN
8
CSI_RST_B
8
DISP0_CONTRAST
7,8
AUX_5V_EN
20
UOK_B
11,18
DOK_B
18
MX6_ONOFF
19
ETH_WOL_INT
12
MICROPHONE_DET
10
SATA_DEVSLP
6
DISP0_WR
9
PCIE_WAKE_B
16
POR_B
13,19,20,21
SATA_RXN
6
SATA_RXP
6
SATA_TXN
6
SATA_TXP
6
PWR_BTN_SNS
19
WDOG_B
21
COMP_INT
14
HDMI_DDC_CLK_IN
7,22
HDMI_DDC_DAT_IN
7,22
Drawing Title:
Size
Document Number
Rev
Date:
Sheet
of
Page Title:
ICAP Classification:
FCP:
FIUO:
PUBI:
SOURCE:SCH-27417 PDF:SPF-27417 C2
MCIMX6DL-SMART DEVICE PLATFORM
D
Friday, November 09, 2012
CPU SIGNAL
325
___ X___
Drawing Title:
Size
Document Number
Rev
Date:
Sheet
of
Page Title:
ICAP Classification:
FCP:
FIUO:
PUBI:
SOURCE:SCH-27417 PDF:SPF-27417 C2
MCIMX6DL-SMART DEVICE PLATFORM
D
Friday, November 09, 2012
CPU SIGNAL
325
___ X___
Drawing Title:
Size
Document Number
Rev
Date:
Sheet
of
Page Title:
ICAP Classification:
FCP:
FIUO:
PUBI:
SOURCE:SCH-27417 PDF:SPF-27417 C2
MCIMX6DL-SMART DEVICE PLATFORM
D
Friday, November 09, 2012
CPU SIGNAL
325
___ X___
i.MX6U - PCIe
U1L
PCIMX6U8DVM10AB
PCIE_RXM
B1
PCIE_TXP
B3
PCIE_RXP
B2
PCIE_VP
H7
PCIE_TXM
A3
PCIE_VPH
G7
PCIE_REXT
A2
PCIE_VPTX
G8
R661 0
R48
0
TP32
R62 33
C635
0.22UF
6.3V
R135 0
R300 0
R87
0
R73 33
R594 0
R38
6.04K
1%
R57 33
R553
0
R82 33
R49
0
R52 33
R588 0
R623
68K
R59 33
R136 0
R120 0
R67 33
R66 0
R653 0
DNP
R125 0
R624
68K
R81 33
R129 0
R126 0
R37
1.6K
1%
U514
NLSV1T34
VCCA
1
VCCB
6
A
2
GND
3
B
4
NC
5
R42 33
R652 0
C667
0.22UF
6.3V
TP509
R51 33
C678
0.22UF
6.3V
R132 0
R91 33
C640
0.22UF
6.3V
R46
0
TP510
R124 0
i.MX6U - DISP; CSI
NVCC_CSI
NVCC_LCD
NVCC_MIPI
NVCC_MIPI
U1D
PCIMX6U8DVM10AB
CSI0_DAT8
N6
CSI0_DAT9
N5
CSI0_DAT10
M1
CSI0_DAT11
M3
CSI0_DAT12
M2
CSI0_DAT13
L1
CSI0_DAT14
M4
CSI0_DAT15
M5
CSI0_DAT16
L4
CSI0_DAT17
L3
CSI0_DAT18
M6
CSI0_DAT19
L6
CSI0_VSYNC
N2
CSI0_PIXCLK
P1
CSI0_MCLK
P4
DI0_PIN4
P25
DISP0_DAT0
P24
DISP0_DAT1
P22
DISP0_DAT2
P23
DISP0_DAT3
P21
DISP0_DAT4
P20
DISP0_DAT5
R25
DISP0_DAT6
R23
DISP0_DAT7
R24
DISP0_DAT8
R22
DISP0_DAT9
T25
DISP0_DAT10
R21
DISP0_DAT11
T23
DISP0_DAT12
T24
DISP0_DAT13
R20
DISP0_DAT14
U25
DISP0_DAT15
T22
DISP0_DAT16
T21
DISP0_DAT17
U24
DISP0_DAT18
V25
DISP0_DAT19
U23
DISP0_DAT20
U22
DISP0_DAT21
T20
DISP0_DAT22
V24
DISP0_DAT23
W24
DI0_PIN3
N20
DI0_DISP_CLK
N19
DI0_PIN2
N25
DI0_PIN15
N21
CSI0_DAT4
N1
CSI0_DAT5
P2
CSI0_DAT6
N4
CSI0_DAT7
N3
CSI0_DATA_EN
P3
CSI_CLK0M
F4
CSI_CLK0P
F3
CSI_D0M
E4
CSI_D0P
E3
CSI_D1M
D1
CSI_D1P
D2
CSI_REXT
D4
DSI_CLK0M
H3
DSI_CLK0P
H4
DSI_D0M
G2
DSI_D0P
G1
DSI_D1M
H2
DSI_D1P
H1
DSI_REXT
G4
R139 0
QZ500
32.768KHZ
1 2
C639
18PF
C651
0.22UF
10V
R72 33
R114 0
C726
1.0UF
C642
0.22UF
10V
R80 33
R60 33
R127 0
R122 0
C624
18PF
R123 0
C668
0.22UF
6.3V
C51
18PF
i.MX6U - USB
U1G
PCIMX6U8DVM10AB
USB_OTG_VBUS
E9
USB_OTG_CHD
B8
USB_OTG_DN
B6
USB_OTG_DP
A6
USB_H1_DP
E10
USB_H1_DN
F10
USB_H1_VBUS
D10
VDDUSB_CAP
F9
R128 0
R88 33
C626
0.22UF
6.3V
R137 0
R134 0
R40 33
C39
DNP
R138 0
R65 33
R69 0
i.MX6U - EIM
NVCC_EIM2 NVCC_EIM0 NVCC_EIM1
U1A
PCIMX6U8DVM10AB
EIM_OE
J24
EIM_WAIT
M25
EIM_BCLK
N22
EIM_LBA
K22
EIM_RW
K20
EIM_EB0
K21
EIM_EB1
K23
EIM_EB2
E22
EIM_EB3
F23
EIM_CS0
H24
EIM_CS1
J23
EIM_A16
H25
EIM_A17
G24
EIM_A18
J22
EIM_A19
G25
EIM_A20
H22
EIM_A21
H23
EIM_A22
F24
EIM_A23
J21
EIM_A24
F25
EIM_A25
H19
EIM_D16
C25
EIM_D17
F21
EIM_D18
D24
EIM_D19
G21
EIM_D20
G20
EIM_D21
H20
EIM_D22
E23
EIM_D23
D25
EIM_D24
F22
EIM_D25
G22
EIM_D26
E24
EIM_D27
E25
EIM_D28
G23
EIM_D29
J19
EIM_D30
J20
EIM_D31
H21
EIM_DA0
L20
EIM_DA1
J25
EIM_DA2
L21
EIM_DA3
K24
EIM_DA4
L22
EIM_DA5
L23
EIM_DA6
K25
EIM_DA7
L25
EIM_DA8
L24
EIM_DA9
M21
EIM_DA10
M22
EIM_DA11
M20
EIM_DA12
M24
EIM_DA13
M23
EIM_DA14
N23
EIM_DA15
N24
C673
DNP
R301 0
R600
0
C622
0.22UF
6.3V
C55
18PF
R171 0
C633
0.22UF
6.3V
R627 0
R79 33
R56 33
R36 0
R610 10M
DNP
R217 0
DNP
R41 33
C638
0.22UF
6.3V
R302 0
DNP
C681
DNP
R90 33
R50
0
R131 0
L13
120OHM
21
R133 0
R605
6.04K
1%
R218 0
DNP
R216
2.2M
C641
0.22UF
6.3V
C606
DNP
i.MX6U - HDMI
U1I
PCIMX6U8DVM10AB
HDMI_REF
J1
HDMI_D0P
K6
HDMI_D1P
J4
HDMI_D1M
J3
HDMI_D0M
K5
HDMI_D2P
K4
HDMI_VP
L7
HDMI_VPH
M7
HDMI_D2M
K3
HDMI_CLKM
J5
HDMI_HPD
K1
HDMI_DDCCEC
K2
HDMI_CLKP
J6
R597 0
i.MX6U
NVCC_ENETNVCC_GPIO
NVCC_SD3NVCC_SD2NVCC_SD1
NVCC_NANDF
U1B
PCIMX6U8DVM10AB
KEY_COL0
W5
KEY_COL1
U7
KEY_COL2
W6
KEY_COL3
U5
KEY_COL4
T6
KEY_ROW0
V6
KEY_ROW1
U6
KEY_ROW2
W4
KEY_ROW3
T7
KEY_ROW4
V5
SD1_CMD
B21
SD1_CLK
D20
SD1_DAT0
A21
SD1_DAT1
C20
SD1_DAT2
E19
SD1_DAT3
F18
SD2_CMD
F19
SD2_CLK
C21
SD2_DAT0
A22
SD2_DAT1
E20
SD2_DAT2
A23
SD2_DAT3
B22
ENET_CRS_DV
U21
ENET_MDC
V20
ENET_MDIO
V23
ENET_REF_CLK
V22
ENET_RXD0
W21
ENET_RX_ER
W23
ENET_RXD1
W22
ENET_TX_EN
V21
ENET_TXD0
U20
ENET_TXD1
W20
GPIO_0
T5
GPIO_1
T4
GPIO_9
T2
GPIO_3
R7
GPIO_6
T3
GPIO_2
T1
GPIO_4
R6
GPIO_5
R4
GPIO_7
R3
GPIO_8
R5
GPIO_16
R2
GPIO_17
R1
GPIO_18
P6
GPIO_19
P5
SD3_DAT7
F13
SD3_DAT6
E13
SD3_DAT5
C13
SD3_DAT4
D13
SD3_CMD
B13
SD3_CLK
D14
SD3_DAT0
E14
SD3_DAT1
F14
SD3_DAT2
A15
SD3_DAT3
B15
SD3_RST
D15
NANDF_CS0
F15
NANDF_CS1
C16
NANDF_CS2
A17
NANDF_CS3
D16
NANDF_ALE
A16
NANDF_CLE
C15
NANDF_WP
E15
NANDF_RB0
B16
NANDF_D0
A18
NANDF_D1
C17
NANDF_D2
F16
NANDF_D3
D17
NANDF_D4
A19
NANDF_D5
B18
NANDF_D6
E17
NANDF_D7
C18
SD4_CLK
E16
SD4_CMD
B17
SD4_DAT0
D18
SD4_DAT1
B19
SD4_DAT2
F17
SD4_DAT3
A20
SD4_DAT4
E18
SD4_DAT5
C19
SD4_DAT6
B20
SD4_DAT7
D19
R74 33
R54 33
R604
200
1%
R44 33
R219 0
DNP
C607
DNP
R86 33
R113 33
R75 10M
DNP
R121 0
R596 0
R167 0
C608
DNP
R70 33
i.MX6U - NC PINS
U1F
PCIMX6U8DVM10AB
NC_G12
G12
NC_B12
B12
NC_A12
A12
NC_B14
B14
NC_A14
A14
NC_C14
C14
NC_G13
G13
NC_B11
B11
NC_A11
A11
NC_B9
B9
NC_A9
A9
NC_B10
B10
NC_A10
A10
NC_E1
E1
NC_E2
E2
NC_F2
F2
NC_F1
F1
NC_N12
N12
C610
DNP
R76 33
R168 0
i.MX6U - CONTROL
NVCC_JTAG
VDD_SNVS_IN
U1C
PCIMX6U8DVM10AB
JTAG_TCK
H5
JTAG_TMS
C3
JTAG_TDI
G5
JTAG_TDO
G6
JTAG_TRST
C2
JTAG_MOD
H6
BOOT_MODE0
C12
BOOT_MODE1
F12
POR
C11
ONOFF
D12
CLK1_P
D7
RTC_XTALI
D9
TEST_MODE
E12
XTALO
B7
XTALI
A7
PMIC_STBY_REQ
F11
PMIC_ON_REQ
D11
CLK1_N
C7
RTC_XTALO
C9
TAMPER
E11
CLK2_P
D5
CLK2_N
C5
C632
0.22UF
6.3V
C625
0.22UF
6.3V
i.MX6U - RGMII
U1K
PCIMX6U8DVM10AB
RGMII_TXC
D21
RGMII_TD0
C22
RGMII_TD1
F20
RGMII_TD2
E21
RGMII_TD3
A24
RGMII_RX_CTL
D22
RGMII_RD0
C24
RGMII_TX_CTL
C23
RGMII_RD1
B23
RGMII_RD2
B24
RGMII_RD3
D23
RGMII_RXC
B25
R84 33
C627
10UF
6.3V
R96
0
TP31
Y1
24MHz
1 4
32
i.MX6U - LVDS
NVCC_LVDS2P5NVCC_LVDS2P5
U1H
PCIMX6U8DVM10AB
LVDS0_CLK_N
V4
LVDS0_CLK_P
V3
LVDS0_TX0_N
U2
LVDS0_TX0_P
U1
LVDS0_TX1_N
U4
LVDS0_TX1_P
U3
LVDS0_TX2_N
V2
LVDS0_TX2_P
V1
LVDS0_TX3_N
W2
LVDS0_TX3_P
W1
LVDS1_CLK_N
Y3
LVDS1_CLK_P
Y4
LVDS1_TX0_N
Y1
LVDS1_TX0_P
Y2
LVDS1_TX1_N
AA2
LVDS1_TX1_P
AA1
LVDS1_TX2_N
AB1
LVDS1_TX2_P
AB2
LVDS1_TX3_N
AA3
LVDS1_TX3_P
AA4
NVCC_LVDS2P5
V7
R619
191.0
1%
R676 0
R656
0
C609
DNP
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Note
1
Note
1
NOTE 1:
Using bit swapping for DATA bus to allow easy pcb routing.
When using data bit swapping the low order bit of each
byte must reside at bit 0 of the byte. The remaining 7 data
bits can be swapped freely. This restriction is for write
leveling calibration.
Example D0 to D0 or D0 to D8, and D1-7 can be swapped.
When swapping byte lanes on 16-bit memories, remember
to move the DQMx, DQSx, and DQSx_B signals for that byte
lane.
Clock access points
Top right
Top left
Bottom under U3
Bottom under U2
GND probe pads
Clock terminators: Place at end of route at each DDR pair
1 GByte
DDR3
GND probe pad
T-point routing
Components allow pin to pin
route length matching
NOTE 2:
Pull down resistor RX3 is added to trace SDCKE0
in Rev B4 by soldering to an existing open via.
Change will be made permanent in layout with the
Rev C board.
DRAM1_ZQ
DRAM_A13
DRAM0_ZQ
DRAM3_ZQ
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_SDQS0
DRAM_A15
DRAM_A10
DRAM_A11
DRAM_A12
DRAM_A13
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_CS0_B
DRAM_RAS_B
DRAM_CAS_B
DRAM_WE_B
DRAM_SDCKE0
DRAM_SDODT0
DRAM_A0
DRAM_A15
DRAM_A14
DRAM_A1
DRAM_SDQS0_B
DRAM_A2DRAM_A2
DRAM_SDQS1
DRAM_SDQS1_B
DRAM_A13
DRAM_A3
DRAM_A4
ZQPAD
DRAM_D8
DRAM_D7
DRAM_D3
DRAM_D5
DRAM_D1
DRAM_D0
DRAM_D6
DRAM_D4
DRAM_D2
DRAM_D11
DRAM_D15
DRAM_D9
DRAM_D13
DRAM_D12
DRAM_D14
DRAM_D10
DRAM_SDQS3
DRAM_SDQS3_B
DRAM_SDQS2
DRAM_SDQS2_B
DRAM_A[15:0]
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_A10
DRAM_A11
DRAM_A12
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_CS0_B
DRAM_RAS_B
DRAM_CAS_B
DRAM_WE_B
DRAM_SDCLK1
DRAM_SDCLK1_B
DRAM_SDCKE0
DRAM_RESET_B
DRAM_SDODT0
DRAM_D0
DRAM_D1
DRAM_D2
DRAM_D3
DRAM_D4
DRAM_D5
DRAM_D6
DRAM_D7
DRAM_D8
DRAM_D9
DRAM_D10
DRAM_D11
DRAM_D12
DRAM_D13
DRAM_D14
DRAM_D15
DRAM_D16
DRAM_D17
DRAM_DQM3
DRAM_DQM2
DRAM_D18
DRAM_D19
DRAM_D20
DRAM_D21
DRAM_D22
DRAM_D23
DRAM_D24
DRAM_D25
DRAM_D26
DRAM_D27
DRAM_D28
DRAM_D29
DRAM_D30
DRAM_D31
DRAM_D32
DRAM_D33
DRAM_D34
DRAM_D35
DRAM_D36
DRAM_D37
DRAM_D38
DRAM_D39
DRAM_D40
DRAM_D41
DRAM_D42
DRAM_D43
DRAM_D44
DRAM_D45
DRAM_D46
DRAM_A15
DRAM_D47
DRAM_D48
DRAM_D49
DRAM_D50
DRAM_D51
DRAM_D52
DRAM_D53
DRAM_D54
DRAM_D55
DRAM_D56
DRAM_D57
DRAM_D58
DRAM_D59
DRAM_D60
DRAM_D61
DRAM_D62
DRAM_D63
DRAM_SDQS0
DRAM_SDQS2
DRAM_SDQS3
DRAM_SDQS4
DRAM_SDQS5
DRAM_SDQS6
DRAM_SDQS7
DRAM_DQM0
DRAM_DQM1
DRAM_DQM2
DRAM_DQM3
DRAM_DQM4
DRAM_DQM5
DRAM_DQM6
DRAM_DQM7
DRAM_SDQS0_B
DRAM_SDQS2_B
DRAM_SDQS3_B
DRAM_SDQS4_B
DRAM_SDQS5_B
DRAM_SDQS6_B
DRAM_SDQS7_B
DRAM_SDQS1
DRAM_SDQS1_B
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_A10
DRAM_A11
DRAM_D19
DRAM_D18
DRAM_D21
DRAM_A12
DRAM_A13
DRAM_D26
DRAM_D30
DRAM_D31
DRAM_D27
DRAM_D29
DRAM_SDBA0
DRAM_D28
DRAM_D25
DRAM_D24
DRAM_D16
DRAM_D22
DRAM_SDBA1
DRAM_SDBA2
DRAM_D17
DRAM_D20
DRAM_D23
DRAM_CS0_B
DRAM_RAS_B
DRAM_CAS_B
DRAM_WE_B
DRAM_SDCLK1
DRAM_SDCLK1_B
DRAM_SDCKE0
DRAM_RESET_B
DRAM_SDODT0
DDR_SDCLK1
DDR_SDCLK1_B
DRAM_A13
DRAM_SDCLK0
DRAM_SDCLK0_B
DRAM_SDCLK1
DRAM_SDCLK1_B
DDR_SDCLK0
DDR_SDCLK0_B
DRAM_SDQS4
DRAM_SDQS4_B
DRAM_SDQS5
DRAM_SDQS5_B
DRAM_D[63:0]
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_A10
DRAM_A11
DRAM_A12
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_CS0_B
DRAM_RAS_B
DRAM_CAS_B
DRAM_WE_B
DRAM_SDCLK0
DRAM_SDCLK0_B
DRAM_SDCKE0
DRAM_RESET_B
DRAM_SDODT0
DRAM_DQM7
DRAM_DQM6
DRAM_D36
DRAM_D45
DRAM_D47
DRAM_D42
DRAM_D34
DRAM_D32
DRAM_D38
DRAM_D39
DRAM_D40
DRAM_D37
DRAM_D44
DRAM_D33
DRAM_D43
DRAM_D35
DRAM_D46
DRAM_D41
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_SDQS6
DRAM_SDQS6_B
DRAM_SDQS7_B
DRAM_SDQS7
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_A10
DRAM_A11
DRAM_A12
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_CS0_B
DRAM_RAS_B
DRAM_CAS_B
DRAM_WE_B
DRAM_SDCLK0
DRAM_SDCLK0_B
DRAM_SDCKE0
DRAM_RESET_B
DRAM_SDODT0
DRAM_DQM4
DRAM_DQM5
DRAM_D53
DRAM_D49
DRAM_D50
DRAM_D58
DRAM_D54
DRAM_D51
DRAM_D55
DRAM_D62
DRAM_D63
DRAM_D56
DRAM_D48
DRAM_D60
DRAM_D57
DRAM_D59
DRAM_D61
DRAM_D52
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_CS0_B
DRAM_RAS_B
DRAM_CAS_B
DRAM_WE_B
DRAM_SDODT0
DRAM_RESET_B
DRAM_DQM0
DRAM2_ZQ
DRAM_DQM1
DRAM_SDCLK0
DRAM_SDCLK0_B
DRAM_SDCLK1
DRAM_SDCLK1_B
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_A10
DRAM_A11
DRAM_A12
DRAM_A13
DRAM_A14
DRAM_A14
DRAM_A15
DRAM_A14
DRAM_A15
DRAM_A14
DRAM_A15
DRAM_A14
DRAM_SDCKE0
GND
DDR_1V5
GND
DDR_1V5
DDR_VREF
GND
DDR_1V5
GND
GND
DDR_1V5
GND
DDR_1V5
GND
DDR_1V5
GND
GND
DDR_1V5
GND
GND
DDR_VREF
DDR_1V5
GNDGND
DDR_VREF
GNDGND
GND
DDR_1V5
GND
GND
GND
DDR_1V5
GND
DDR_VREF
GND
DDR_VREF
GNDGND
GND
GND
GNDGND
GND
GND
Drawing Title:
Size
Document Number
Rev
Date:
Sheet
of
Page Title:
ICAP Classification:
FCP:
FIUO:
PUBI:
SOURCE:SCH-27417 PDF:SPF-27417 C2
MCIMX6DL-SMART DEVICE PLATFORM
C
Friday, November 09, 2012
DDR3 MEMORY
425
___
X
___
Drawing Title:
Size
Document Number
Rev
Date:
Sheet
of
Page Title:
ICAP Classification:
FCP:
FIUO:
PUBI:
SOURCE:SCH-27417 PDF:SPF-27417 C2
MCIMX6DL-SMART DEVICE PLATFORM
C
Friday, November 09, 2012
DDR3 MEMORY
425
___
X
___
Drawing Title:
Size
Document Number
Rev
Date:
Sheet
of
Page Title:
ICAP Classification:
FCP:
FIUO:
PUBI:
SOURCE:SCH-27417 PDF:SPF-27417 C2
MCIMX6DL-SMART DEVICE PLATFORM
C
Friday, November 09, 2012
DDR3 MEMORY
425
___
X
___
C616
0.22UF
16V
R119 240
R602 10.0K
C41
0.22UF
16V
TP16
T36
C58
0.22UF
16V
C47
0.22UF
16V
T59
SH20
0
T2
T60
T30 T35T28
C42
0.22UF
16V
T75
C35
22UF
6.3V
T55
T27
C620
0.22UF
16V
T53
TP17
C70
0.22UF
16V
C733
0.22UF
16V
R43
200
1%
T50
SH19
0
C49
22UF
6.3V
C618
0.22UF
16V
T37
T3
C46
0.22UF
16V
i.MX6U - DDR
U1J
PCIMX6U8DVM10AB
DRAM_VREF
AC2
DRAM_D40
Y19
DRAM_D41
AB20
DRAM_D42
AB21
DRAM_D43
AD21
DRAM_D44
Y20
DRAM_D45
AA20
DRAM_D46
AE21
DRAM_D47
AC21
DRAM_SDQS5
AD20
DRAM_SDQS5
AE20
DRAM_DQM5
AC20
DRAM_D32
AA17
DRAM_D33
AA18
DRAM_D34
AC18
DRAM_D35
AE19
DRAM_D36
Y17
DRAM_D37
Y18
DRAM_D38
AB19
DRAM_D39
AC19
DRAM_DQM4
AB18
DRAM_SDQS4
AD18
DRAM_SDQS4
AE18
DRAM_D24
AE9
DRAM_D25
Y10
DRAM_D26
AE11
DRAM_D27
AB11
DRAM_D28
AC9
DRAM_D29
AD9
DRAM_SDQS3
AC10
DRAM_SDQS3
AB10
DRAM_D30
AD11
DRAM_D31
AC11
DRAM_DQM3
AE10
DRAM_D16
AB7
DRAM_D17
AA8
DRAM_D18
AB9
DRAM_D19
Y9
DRAM_D20
Y7
DRAM_D21
Y8
DRAM_D22
AC8
DRAM_SDQS2
AD8
DRAM_SDQS2
AE8
DRAM_D23
AA9
DRAM_DQM2
AB8
DRAM_A0
AC14
DRAM_A1
AB14
DRAM_A2
AA14
DRAM_A3
Y14
DRAM_A4
W14
DRAM_A5
AE13
DRAM_A6
AC13
DRAM_A7
Y13
DRAM_A8
AB13
DRAM_A9
AE12
DRAM_A10
AA15
DRAM_A11
AC12
DRAM_A12
AD12
DRAM_A13
AC17
DRAM_A14
AA12
DRAM_A15
Y12
ZQPAD
AE17
DRAM_CAS
AE16
DRAM_CS0
Y16
DRAM_CS1
AD17
DRAM_RAS
AB15
DRAM_RESET
Y6
DRAM_SDBA0
AC15
DRAM_SDBA1
Y15
DRAM_SDCLK_0
AD15
DRAM_SDCLK_0
AE15
DRAM_SDBA2
AB12
DRAM_SDCKE0
Y11
DRAM_SDCLK_1
AD14
DRAM_SDCLK_1
AE14
DRAM_SDCKE1
AA11
DRAM_SDODT0
AC16
DRAM_SDODT1
AB17
DRAM_SDWE
AB16
DRAM_D0
AD2
DRAM_D1
AE2
DRAM_D2
AC4
DRAM_D3
AA5
DRAM_D4
AC1
DRAM_D5
AD1
DRAM_SDQS0
AE3
DRAM_SDQS0
AD3
DRAM_D6
AB4
DRAM_D7
AE4
DRAM_DQM0
AC3
DRAM_D8
AD5
DRAM_D9
AE5
DRAM_D10
AA6
DRAM_D11
AE7
DRAM_D12
AB5
DRAM_D13
AC5
DRAM_D14
AB6
DRAM_SDQS1
AD6
DRAM_SDQS1
AE6
DRAM_D15
AC7
DRAM_DQM1
AC6
DRAM_D48
AC22
DRAM_D49
AE22
DRAM_D50
AE24
DRAM_D51
AC24
DRAM_D52
AB22
DRAM_D53
AC23
DRAM_D54
AD25
DRAM_D55
AC25
DRAM_SDQS6
AD23
DRAM_SDQS6
AE23
DRAM_DQM6
AD24
DRAM_D56
AB25
DRAM_SDQS7
AA25
DRAM_SDQS7
AA24
DRAM_D57
AA21
DRAM_D58
Y25
DRAM_D59
Y22
DRAM_D60
AB23
DRAM_DQM7
Y21
DRAM_D61
AA23
DRAM_D62
Y23
DRAM_D63
W25
NVCC_DRAM_8
V14
NVCC_DRAM_9
V15
NVCC_DRAM_10
V16
NVCC_DRAM_11
V17
NVCC_DRAM_12
V18
NVCC_DRAM_13
V9
NVCC_DRAM_1
R18
NVCC_DRAM_2
T18
NVCC_DRAM_3
U18
NVCC_DRAM_4
V10
NVCC_DRAM_5
V11
NVCC_DRAM_6
V12
NVCC_DRAM_7
V13
T52
C59
0.22UF
16V
T25T61
T32
T15T5 T16
C73
0.22UF
16V
C619
0.22UF
6.3V
R599 240
C76
0.22UF
16V
C43
0.22UF
16V
T34
T12 T65
2G_DDR3_SDRAM_128MX16
U3
MT41K128M16JT
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
BA0
M2
BA1
N8
BA2
M3
VDD1
B2
VDD2
D9
VDD3
G7
VDD4
K2
VDD5
K8
VDD6
N1
VDD7
N9
VDD8
R1
VDD9
R9
VDDQ1
A1
VDDQ2
A8
VDDQ3
C1
VDDQ4
C9
VSS1
A9
VSS2
B3
VSS3
E1
VSS4
G8
VSS5
J2
VSS6
J8
VSS7
M1
VSS8
M9
VSS9
P1
VSS10
P9
VSS11
T1
VSS12
T9
VSSQ1
B1
VSSQ2
B9
VSSQ3
D1
VSSQ4
D8
VSSQ5
E2
NC_L1
L1
NC_L9
L9
NC_M7
M7
NC_T7
T7
DQ0
E3
DQ1
F7
DQ2
F2
DQ3
F8
DQ4
H3
DQ5
H8
DQ6
G2
DQ7
H7
A10/AP
L7
A11
R7
A12/BC
N7
LDQS
F3
LDQS
G3
UDQS
C7
UDQS
B7
DQ8
D7
DQ9
C3
DQ10
C8
DQ11
C2
DQ12
A7
DQ13
A2
DQ14
B8
DQ15
A3
VDDQ5
D2
VDDQ6
E9
VDDQ7
F1
VDDQ8
H2
VDDQ9
H9
VSSQ6
E8
VSSQ7
F9
VSSQ8
G1
VSSQ9
G9
A13
T3
NC_J9
J9
NC_J1
J1
CK
J7
CK
K7
CKE
K9
CS
L2
RAS
J3
CAS
K3
WE
L3
RESET
T2
ODT
K1
VREFCA
M8
VREFDQ
H1
ZQ
L8
LDM
E7
UDM
D3
T63 T66
R107 240
1%
T8
T62
T39
C52
0.22UF
16V
C728
0.22UF
6.3V
C735
0.22UF
16V
C72
0.22UF
16V
C74
0.22UF
16V
T64
T49
T13
T38
T11
T51
C37
0.22UF
16V
C53
0.22UF
16V
T68
T29
C653
0.22UF
16V
C77
22UF
6.3V
C736
0.22UF
16V
T44
T1 T54 T18
T45
C79
22UF
6.3V
T40
C64
0.22UF
16V
T9
T42
T58
C727
0.22UF
6.3V
T22
T57
TP15
T74
C78
22UF
6.3V
C718
0.22UF
16V
R89 240
C737
0.22UF
16V
T26
C621
0.1UF
16V
C48
0.22UF
6.3V
T20
C44
0.22UF
16V
2G_DDR3_SDRAM_128MX16
U2
MT41K128M16JT
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
BA0
M2
BA1
N8
BA2
M3
VDD1
B2
VDD2
D9
VDD3
G7
VDD4
K2
VDD5
K8
VDD6
N1
VDD7
N9
VDD8
R1
VDD9
R9
VDDQ1
A1
VDDQ2
A8
VDDQ3
C1
VDDQ4
C9
VSS1
A9
VSS2
B3
VSS3
E1
VSS4
G8
VSS5
J2
VSS6
J8
VSS7
M1
VSS8
M9
VSS9
P1
VSS10
P9
VSS11
T1
VSS12
T9
VSSQ1
B1
VSSQ2
B9
VSSQ3
D1
VSSQ4
D8
VSSQ5
E2
NC_L1
L1
NC_L9
L9
NC_M7
M7
NC_T7
T7
DQ0
E3
DQ1
F7
DQ2
F2
DQ3
F8
DQ4
H3
DQ5
H8
DQ6
G2
DQ7
H7
A10/AP
L7
A11
R7
A12/BC
N7
LDQS
F3
LDQS
G3
UDQS
C7
UDQS
B7
DQ8
D7
DQ9
C3
DQ10
C8
DQ11
C2
DQ12
A7
DQ13
A2
DQ14
B8
DQ15
A3
VDDQ5
D2
VDDQ6
E9
VDDQ7
F1
VDDQ8
H2
VDDQ9
H9
VSSQ6
E8
VSSQ7
F9
VSSQ8
G1
VSSQ9
G9
A13
T3
NC_J9
J9
NC_J1
J1
CK
J7
CK
K7
CKE
K9
CS
L2
RAS
J3
CAS
K3
WE
L3
RESET
T2
ODT
K1
VREFCA
M8
VREFDQ
H1
ZQ
L8
LDM
E7
UDM
D3
T24
C717
0.22UF
16V
T56
2G_DDR3_SDRAM_128MX16
U5
MT41K128M16JT
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
BA0
M2
BA1
N8
BA2
M3
VDD1
B2
VDD2
D9
VDD3
G7
VDD4
K2
VDD5
K8
VDD6
N1
VDD7
N9
VDD8
R1
VDD9
R9
VDDQ1
A1
VDDQ2
A8
VDDQ3
C1
VDDQ4
C9
VSS1
A9
VSS2
B3
VSS3
E1
VSS4
G8
VSS5
J2
VSS6
J8
VSS7
M1
VSS8
M9
VSS9
P1
VSS10
P9
VSS11
T1
VSS12
T9
VSSQ1
B1
VSSQ2
B9
VSSQ3
D1
VSSQ4
D8
VSSQ5
E2
NC_L1
L1
NC_L9
L9
NC_M7
M7
NC_T7
T7
DQ0
E3
DQ1
F7
DQ2
F2
DQ3
F8
DQ4
H3
DQ5
H8
DQ6
G2
DQ7
H7
A10/AP
L7
A11
R7
A12/BC
N7
LDQS
F3
LDQS
G3
UDQS
C7
UDQS
B7
DQ8
D7
DQ9
C3
DQ10
C8
DQ11
C2
DQ12
A7
DQ13
A2
DQ14
B8
DQ15
A3
VDDQ5
D2
VDDQ6
E9
VDDQ7
F1
VDDQ8
H2
VDDQ9
H9
VSSQ6
E8
VSSQ7
F9
VSSQ8
G1
VSSQ9
G9
A13
T3
NC_J9
J9
NC_J1
J1
CK
J7
CK
K7
CKE
K9
CS
L2
RAS
J3
CAS
K3
WE
L3
RESET
T2
ODT
K1
VREFCA
M8
VREFDQ
H1
ZQ
L8
LDM
E7
UDM
D3
T46
T6
C67
0.22UF
16V
R635
10.0K
1%
T41
C647
0.22UF
16V
C45
0.22UF
16V
T70
T14
T72
R99 240
C617
0.22UF
16V
T31
C734
0.22UF
16V
C731
0.22UF
16V
T47
T4
C75
0.22UF
16V
C613
0.22UF
16V
C615
0.22UF
16V
T21
T48
SH21
0
C732
0.22UF
16V
C56
0.22UF
16V
T71
T43
T67
C36
22UF
6.3V
C666
0.22UF
16V
T7
C57
0.22UF
16V
T73
T69 T17
SH18
0
R118
200
1%
2G_DDR3_SDRAM_128MX16
U4
MT41K128M16JT
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
BA0
M2
BA1
N8
BA2
M3
VDD1
B2
VDD2
D9
VDD3
G7
VDD4
K2
VDD5
K8
VDD6
N1
VDD7
N9
VDD8
R1
VDD9
R9
VDDQ1
A1
VDDQ2
A8
VDDQ3
C1
VDDQ4
C9
VSS1
A9
VSS2
B3
VSS3
E1
VSS4
G8
VSS5
J2
VSS6
J8
VSS7
M1
VSS8
M9
VSS9
P1
VSS10
P9
VSS11
T1
VSS12
T9
VSSQ1
B1
VSSQ2
B9
VSSQ3
D1
VSSQ4
D8
VSSQ5
E2
NC_L1
L1
NC_L9
L9
NC_M7
M7
NC_T7
T7
DQ0
E3
DQ1
F7
DQ2
F2
DQ3
F8
DQ4
H3
DQ5
H8
DQ6
G2
DQ7
H7
A10/AP
L7
A11
R7
A12/BC
N7
LDQS
F3
LDQS
G3
UDQS
C7
UDQS
B7
DQ8
D7
DQ9
C3
DQ10
C8
DQ11
C2
DQ12
A7
DQ13
A2
DQ14
B8
DQ15
A3
VDDQ5
D2
VDDQ6
E9
VDDQ7
F1
VDDQ8
H2
VDDQ9
H9
VSSQ6
E8
VSSQ7
F9
VSSQ8
G1
VSSQ9
G9
A13
T3
NC_J9
J9
NC_J1
J1
CK
J7
CK
K7
CKE
K9
CS
L2
RAS
J3
CAS
K3
WE
L3
RESET
T2
ODT
K1
VREFCA
M8
VREFDQ
H1
ZQ
L8
LDM
E7
UDM
D3
T33
T10 T23
T19
C614
0.22UF
16V
C71
0.22UF
16V
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Layout:
50ohm, SD singals(SD_DATAx, SD_CMD, SD_CLK) control.
4MB SPI NOR FLASH8GB eMMC MEMORY
EMMC_VDDI
SPI_NOR_HOLD_B
EMMC_3V3
SPI_NOR_WP
GEN_3V3
GND
GND
GND
GND
GEN_3V3 GEN_3V3
GND
GEN_3V3
GND
GND
GEN_3V3
EMMCIO_3V3
SD4_DATA0
3
SD4_DATA1
3
SD4_DATA2
3
SD4_DATA3
3
SD4_DATA4
3
SD4_DATA5
3
SD4_DATA6
3
SD4_DATA7
3
SPINOR_MISO
22
SPINOR_MOSI
22
SPINOR_CLK
22
SPINOR_CS0
22
SD4_CLK
3
SD4_CMD
3
Drawing Title:
Size
Document Number
Rev
Date:
Sheet
of
Page Title:
ICAP Classification:
FCP:
FIUO:
PUBI:
SOURCE:SCH-27417 PDF:SPF-27417 C2
MCIMX6DL-SMART DEVICE PLATFORM
C
Friday, November 09, 2012
eMMC, SPI NOR FLASH
525
___
X
___
Drawing Title:
Size
Document Number
Rev
Date:
Sheet
of
Page Title:
ICAP Classification:
FCP:
FIUO:
PUBI:
SOURCE:SCH-27417 PDF:SPF-27417 C2
MCIMX6DL-SMART DEVICE PLATFORM
C
Friday, November 09, 2012
eMMC, SPI NOR FLASH
525
___
X
___
Drawing Title:
Size
Document Number
Rev
Date:
Sheet
of
Page Title:
ICAP Classification:
FCP:
FIUO:
PUBI:
SOURCE:SCH-27417 PDF:SPF-27417 C2
MCIMX6DL-SMART DEVICE PLATFORM
C
Friday, November 09, 2012
eMMC, SPI NOR FLASH
525
___
X
___
C19
0.1UF
6.3V
R20
10.0K
R643
200K
C22
4.7UF
6.3V
C83
0.1UF
16V
C26
4.7UF
6.3V
C25
0.1UF
6.3V
C27
0.1UF
6.3V
R149
10.0K
U512B
SDIN5C2-8G
NC_A4
A4
NC_A6
A6
NC_A9
A9
NC_A11
A11
NC_B2
B2
NC_B13
B13
NC_D1
D1
NC_D14
D14
NC_H1
H1
NC_H2
H2
NC_H6
H6
NC_H7
H7
NC_H8
H8
NC_H9
H9
NC_H10
H10
NC_H11
H11
NC_H12
H12
NC_H13
H13
NC_H14
H14
NC_J1
J1
NC_J7
J7
NC_J8
J8
NC_J9
J9
NC_J10
J10
NC_J11
J11
NC_J12
J12
NC_J14
J14
NC_J13
J13
NC_K1
K1
NC_R1
R1
NC_R2
R2
NC_R3
R3
NC_R5
R5
NC_R12
R12
NC_R14
R14
NC_R13
R13
NC_T1
T1
NC_T2
T2
NC_T3
T3
NC_T5
T5
NC_T12
T12
NC_T13
T13
NC_T14
T14
NC_U1
U1
NC_U2
U2
NC_U3
U3
NC_U6
U6
NC_U7
U7
NC_U10
U10
NC_U12
U12
NC_U13
U13
NC_U14
U14
NC_V1
V1
NC_V2
V2
NC_V3
V3
NC_V12
V12
NC_V13
V13
NC_V14
V14
NC_W1
W1
NC_W2
W2
NC_W3
W3
NC_W7
W7
NC_W8
W8
NC_W9
W9
NC_W10
W10
NC_W11
W11
NC_W12
W12
NC_W13
W13
NC_W14
W14
NC_Y1
Y1
NC_Y3
Y3
NC_Y6
Y6
NC_Y7
Y7
NC_Y8
Y8
NC_Y9
Y9
NC_Y10
Y10
NC_Y11
Y11
NC_Y12
Y12
NC_Y13
Y13
NC_Y14
Y14
NC_AA1
AA1
NC_AA2
AA2
NC_AA7
AA7
NC_AA8
AA8
NC_AA9
AA9
NC_AA10
AA10
NC_AA11
AA11
NC_AA12
AA12
NC_AA13
AA13
NC_AA14
AA14
NC_AE1
AE1
NC_AE14
AE14
NC_AG2
AG2
NC_AG13
AG13
NC_AH4
AH4
NC_AH6
AH6
NC_P12
P12
NC_P13
P13
NC_P10
P10
NC_P3
P3
NC_P2
P2
NC_P1
P1
NC_N14
N14
NC_N13
N13
NC_N12
N12
NC_N10
N10
NC_K3
K3
NC_K5
K5
NC_K7
K7
NC_K8
K8
NC_K9
K9
NC_K10
K10
NC_K11
K11
NC_K12
K12
NC_K13
K13
NC_K14
K14
NC_L1
L1
NC_L2
L2
NC_L3
L3
NC_L4
L4
NC_L12
L12
NC_L13
L13
NC_L14
L14
NC_M1
M1
NC_M2
M2
NC_M3
M3
NC_M5
M5
NC_M8
M8
NC_M9
M9
NC_M10
M10
NC_M12
M12
NC_M13
M13
NC_M14
M14
NC_N1
N1
NC_N2
N2
NC_N3
N3
NC_P14
P14
NC_AH9
AH9
NC_AH11
AH11
C20
0.1UF
6.3V
U14
M25P32-VMW6TG
S
1
Q
2
W/VPP
3
VSS
4
D
5
C
6
HOLD
7
VCC
8
C21
0.1UF
6.3V
SH11
SOLDER SHORT
C23
0.1UF
6.3V
SH8
SOLDER SHORT
R646
10.0K
DNP
U512A
SDIN5C2-8G
DAT7
J6
VCCQ3
K6
VCC3
T10
VCC4
U9
VCCQ5
Y4
VCCQ4
W4
VSSQ3
K4
VSSQ2
AA6
VCCQ2
AA5
VSS3
R10
VSS4
U8
RESET
U5
VSS2
P5
VCCQ1
AA3
VSS1
M7
VSSQ5
Y5
VSSQ4
Y2
DAT6
J5
VCC1
M6
VCC2
N5
CMD
W5
VSSQ1
AA4
CLK
W6
DAT0
H3
DAT1
H4
DAT2
H5
DAT3
J2
DAT4
J3
DAT5
J4
VDDI
K2
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