5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_A10
DRAM_A11
DRAM_A12
DRAM_A13
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_A10
DRAM_A11
DRAM_A12
DRAM_A13
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_A10
DRAM_A11
DRAM_A12
DRAM_A13
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_A10
DRAM_A11
DRAM_A12
DRAM_A13
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_A10
DRAM_A11
DRAM_A12
DRAM_A13
DRAM_A[13..0]
DRAM_D0
DRAM_D1
DRAM_D2
DRAM_D3
DRAM_D4
DRAM_D5
DRAM_D6
DRAM_D7
DRAM_D8
DRAM_D9
DRAM_D10
DRAM_D11
DRAM_D12
DRAM_D13
DRAM_D14
DRAM_D15
DRAM_D16
DRAM_D17
DRAM_D18
DRAM_D19
DRAM_D20
DRAM_D21
DRAM_D22
DRAM_D23
DRAM_D24
DRAM_D25
DRAM_D26
DRAM_D27
DRAM_D28
DRAM_D29
DRAM_D30
DRAM_D31
DRAM_D[15..0]
DRAM_D[31..16]
DRAM_CS0
DRAM_CS1
EIM_SDBA0
EIM_SDBA1
EIM_SDBA2
DRAM_RAS
DRAM_CAS
DRAM_SDWE
DRAM_SDCKE0
DRAM_SDCKE1
EIM_SDODT0
EIM_SDODT1
DRAM_RESET
DRAM_CAL_MX53
DRAM_SDQS0
DRAM_SDQS0_B
DRAM_SDQS1
DRAM_SDQS1_B
DRAM_SDQS2
DRAM_SDQS2_B
DRAM_SDQS3
DRAM_DQM0
DRAM_DQM1
DRAM_DQM2
DRAM_DQM3
DRAM_SDQS3_B
EIM_SDBA0
EIM_SDBA1
EIM_SDBA2
EIM_SDBA0
EIM_SDBA1
EIM_SDBA2
EIM_SDBA0
EIM_SDBA1
EIM_SDBA2
EIM_SDBA0
EIM_SDBA1
EIM_SDBA2
DRAM_RAS
DRAM_CAS
DRAM_RAS
DRAM_CAS
DRAM_RAS
DRAM_CAS
DRAM_RAS
DRAM_CAS
DRAM_SDWE
DRAM_SDWE
DRAM_SDWE
DRAM_SDWE
DRAM_SDCKE0
DRAM_SDCKE0
DRAM_SDCKE1
DRAM_SDCKE1
DRAM_RESET
DRAM_RESET
DRAM_RESET
DRAM_RESET
DRAM_CAL_DDRA
DRAM_CAL_DDRB
DRAM_CAL_DDRD
DRAM_CAL_DDRC
DRAM_CS0
DRAM_CS0
DRAM_SDCLK_0
DRAM_SDCLK_0_B
DRAM_SDCLK_1
DRAM_SDCLK_1_B
EIM_SDODT0
EIM_SDODT1
DRAM_DQM1
DRAM_DQM0
DRAM_DQM1
DRAM_DQM0
DRAM_DQM2
DRAM_DQM3
DRAM_DQM2
DRAM_DQM3
DRAM_SDQS0
DRAM_SDQS0_B
DRAM_SDQS1
DRAM_SDQS1_B
DRAM_SDQS0_B
DRAM_SDQS0
DRAM_SDQS1
DRAM_SDQS1_B
DRAM_SDQS3_B
DRAM_SDQS2
DRAM_SDQS2_B
DRAM_SDQS3 DRAM_SDQS3_B
DRAM_SDQS2
DRAM_SDQS3
DRAM_SDQS2_B
DRAM_CLK0
DRAM_CLK0#
DRAM_CLK1
DRAM_CLK1#
DRAM_SDCLK_0
DRAM_SDCLK_0_B
DRAM_SDCLK_1
DRAM_SDCLK_1_B
DRAM_D[31..16] DRAM_D[31..16]
DRAM_D[15..0]
DRAM_D[15..0]
EIM_SDODT0
EIM_SDODT1
DRAM_SDCLK_0
DRAM_SDCLK_0_B
DRAM_SDCLK_1
DRAM_SDCLK_1_B
DRAM_CS1
DRAM_CS1
DRAM_SDCLK_1_B
DRAM_SDCLK_0
DRAM_SDCLK_0_B
DRAM_SDCLK_1
DRAM_D7
DRAM_D15
DRAM_D8
DRAM_D9
DRAM_D10
DRAM_D11
DRAM_D12
DRAM_D13
DRAM_D14
DRAM_D0
DRAM_D1
DRAM_D2
DRAM_D3
DRAM_D4
DRAM_D5
DRAM_D6
DRAM_D23
DRAM_D31
DRAM_D24
DRAM_D25
DRAM_D26
DRAM_D27
DRAM_D28
DRAM_D29
DRAM_D30
DRAM_D16
DRAM_D17
DRAM_D18
DRAM_D19
DRAM_D20
DRAM_D21
DRAM_D22
DRAM_D31
DRAM_D22
DRAM_D19
DRAM_D27
DRAM_D30
DRAM_D18
DRAM_D24
DRAM_D21
DRAM_D29
DRAM_D17
DRAM_D20
DRAM_D25
DRAM_D28
DRAM_D16
DRAM_D23
DRAM_D26
DRAM_D3
DRAM_D10
DRAM_D1
DRAM_D14
DRAM_D6
DRAM_D7
DRAM_D15
DRAM_D8
DRAM_D9
DRAM_D11
DRAM_D12
DRAM_D13
DRAM_D0
DRAM_D2
DRAM_D5
DRAM_D4
DDR_VREF
DDR_VREF
DDR_VREF
DDR_VREF
DDRQ_1.5V DDR_VREFDDR_VREF
DDR_VREF
DDR_1.5V
DDR_1.5V
DDR_1.5V
DDR_1.5V DDR_1.5V
DDR_1.5V
DDR_1.5V
DDR_1.5V
DDRQ_1.5V
DDRQ_1.5V
DDRQ_1.5V
DDRQ_1.5V
DDRQ_1.5V
DDRQ_1.5V
DDRQ_1.5V
DDRQ_1.5V
Title
Size Document Number Rev
Date: Sheet
of
CAP100
S1
IMX53 DDR3
C
312Tuesday, March 13, 2012
Title
Size Document Number Rev
Date: Sheet of
CAP100
S1
IMX53 DDR3
C
312Tuesday, March 13, 2012
Title
Size Document Number Rev
Date: Sheet of
CAP100
S1
IMX53 DDR3
C
312Tuesday, March 13, 2012
1) Data pins can be swapped
within each byte
2) Data bytes can be
swapped
3) DQMx and DQSx must
follow each byte
When swapping bytes 0 or 1
into 2 or 3, must then use
32 bit access. Cannot use
16-bit access.
NOTE:
DDR data pins can be
swapped for improved
routing according to the
following rules:
USE: ELPIDA EDJ2116DASE-DJ-F or MICRON MT41J128M16HA-15E
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
BA0
M2
BA1
N8
BA2
M3
VDD1
B2
VDD2
D9
VDD3
G7
VDD4
K2
VDD5
K8
VDD6
N1
VDD7
N9
VDD8
R1
VDD9
R9
VDDQ1
A1
VDDQ2
A8
VDDQ3
C1
VDDQ4
C9
VSS1
A9
VSS2
B3
VSS3
E1
VSS4
G8
VSS5
J2
VSS6
J8
VSS7
M1
VSS8
M9
VSS9
P1
VSS10
P9
VSS11
T1
VSS12
T9
VSSQ1
B1
VSSQ2
B9
VSSQ3
D1
VSSQ4
D8
VSSQ5
E2
NC_L1
L1
NC_L9
L9
NC_M7
M7
NC_T7
T7
DQ0
E3
DQ1
F7
DQ2
F2
DQ3
F8
DQ4
H3
DQ5
H8
DQ6
G2
DQ7
H7
A10/AP
L7
A11
R7
A12/BC
N7
LDQS
F3
LDQS
G3
UDQS
C7
UDQS
B7
DQ8
D7
DQ9
C3
DQ10
C8
DQ11
C2
DQ12
A7
DQ13
A2
DQ14
B8
DQ15
A3
VDDQ5
D2
VDDQ6
E9
VDDQ7
F1
VDDQ8
H2
VDDQ9
H9
VSSQ6
E8
VSSQ7
F9
VSSQ8
G1
VSSQ9
G9
A13
T3
NC_J9
J9
NC_J1
J1
CK
J7
CK
K7
CKE
K9
CS
L2
RAS
J3
CAS
K3
WE
L3
RESET
T2
ODT
K1
VREFCA
M8
VREFDQ
H1
ZQ
L8
LDM
E7
UDM
D3
2G_DDR3_SDRAM_128MX16
U5
MT41J128M16HA-15E
2G_DDR3_SDRAM_128MX16
U5
MT41J128M16HA-15E
C101
0.01UF
C101
0.01UF
R18
240
R18
240
C74
0.01UF
C74
0.01UF
C83
0.1UF
C83
0.1UF
C110
0.1UF
C110
0.1UF
DRAM_A0
M19
DRAM_A1
L21
DRAM_A2
M20
DRAM_A3
N20
DRAM_A5
N21
DRAM_A6
M22
DRAM_A7
N22
DRAM_A8
N23
DRAM_A9
M21
DRAM_A10
K19
DRAM_A11
L22
DRAM_A12
L20
DRAM_A13
L23
DRAM_A14
N18
DRAM_SDBA0
R19
DRAM_SDBA1
P20
DRAM_RAS
J19
DRAM_CAS
L18
DRAM_SDWE
L19
DRAM_SDCKE0
H19
DRAM_SDCKE1
T19
DRAM_SDCLK_0
K23
DRAM_SDCLK_0_B
K22
DRAM_CS0
K18
DRAM_CS1
P19
DRAM_SDQS0
H23
DRAM_SDQS3
Y22
DRAM_D0
H20
DRAM_D1
G21
DRAM_D2
J21
DRAM_D3
G20
DRAM_D4
J23
DRAM_D5
G23
DRAM_D6
J22
DRAM_D7
G22
DRAM_D8
E21
DRAM_D9
D21
DRAM_D10
E22
DRAM_D11
D20
DRAM_D12
E23
DRAM_D13
C23
DRAM_D14
F23
DRAM_D15
C22
DRAM_D16
U20
DRAM_D17
T21
DRAM_D18
U21
DRAM_D19
R21
DRAM_D20
U23
DRAM_D21
R22
DRAM_D22
U22
DRAM_D23
R23
DRAM_D24
Y20
DRAM_D25
W21
DRAM_D26
Y21
DRAM_D27
W22
DRAM_D28
AA23
DRAM_D29
V23
DRAM_D30
AA22
DRAM_D31
W23
DRAM_DQM0
H21
DRAM_DQM1
E20
DRAM_DQM2
T20
DRAM_DQM3
W20
DRAM_SDBA2
N19
DRAM_SDQS0_B
H22
DRAM_SDQS1
D23
DRAM_SDQS2
T22
DRAM_SDQS3_B
Y23
DRAM_SDQS2_B
T23
DRAM_SDQS1_B
D22
DRAM_SDODT0
J18
DRAM_SDODT1
R18
DRAM_SDCLK_1_B
P23
DRAM_SDCLK_1
P22
DRAM_RESET
P18
DRAM_CALIBRATION
M23
DRAM_A15
M18
DRAM_A4
K20
DDR_VREF
L17
i.MX53 - DDR
U1J
i.MX53 - DDR
U1J
C106
10UF
C106
10UF
C120
0.1UF
C120
0.1UF
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
BA0
M2
BA1
N8
BA2
M3
VDD1
B2
VDD2
D9
VDD3
G7
VDD4
K2
VDD5
K8
VDD6
N1
VDD7
N9
VDD8
R1
VDD9
R9
VDDQ1
A1
VDDQ2
A8
VDDQ3
C1
VDDQ4
C9
VSS1
A9
VSS2
B3
VSS3
E1
VSS4
G8
VSS5
J2
VSS6
J8
VSS7
M1
VSS8
M9
VSS9
P1
VSS10
P9
VSS11
T1
VSS12
T9
VSSQ1
B1
VSSQ2
B9
VSSQ3
D1
VSSQ4
D8
VSSQ5
E2
NC_L1
L1
NC_L9
L9
NC_M7
M7
NC_T7
T7
DQ0
E3
DQ1
F7
DQ2
F2
DQ3
F8
DQ4
H3
DQ5
H8
DQ6
G2
DQ7
H7
A10/AP
L7
A11
R7
A12/BC
N7
LDQS
F3
LDQS
G3
UDQS
C7
UDQS
B7
DQ8
D7
DQ9
C3
DQ10
C8
DQ11
C2
DQ12
A7
DQ13
A2
DQ14
B8
DQ15
A3
VDDQ5
D2
VDDQ6
E9
VDDQ7
F1
VDDQ8
H2
VDDQ9
H9
VSSQ6
E8
VSSQ7
F9
VSSQ8
G1
VSSQ9
G9
A13
T3
NC_J9
J9
NC_J1
J1
CK
J7
CK
K7
CKE
K9
CS
L2
RAS
J3
CAS
K3
WE
L3
RESET
T2
ODT
K1
VREFCA
M8
VREFDQ
H1
ZQ
L8
LDM
E7
UDM
D3
2G_DDR3_SDRAM_128MX16
U3
MT41J128M16HA-15E
2G_DDR3_SDRAM_128MX16
U3
MT41J128M16HA-15E
C75
0.1UF
C75
0.1UF
C90
10UF
C90
10UF
C111
0.1UF
C111
0.1UF
R11
200
R11
200
C105
0.01UF
C105
0.01UF
C107
0.1UF
C107
0.1UF
C67
0.1UF
C67
0.1UF
C117
0.1UF
C117
0.1UF
C80
0.1UF
C80
0.1UF
C91
0.1UF
C91
0.1UF
R19
240
R19
240
R9
470
R9
470
C84
0.1UF
C84
0.1UF
C71
0.1UF
C71
0.1UF
C100
0.1UF
C100
0.1UF
R130 R130
R10
200
R10
200
C96
0.01UF
C96
0.01UF
C113
0.1UF
C113
0.1UF
C89
0.01UF
C89
0.01UF
R12
240
R12
240
C85
0.01UF
C85
0.01UF
C98
10UF
C98
10UF
C82
0.1UF
C82
0.1UF
C116
10UF
C116
10UF
C109
0.1UF
C109
0.1UF
C122
10UF
C122
10UF
C76
0.01UF
C76
0.01UF
C69
0.1UF
C69
0.1UF
C119
0.1UF
C119
0.1UF
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
BA0
M2
BA1
N8
BA2
M3
VDD1
B2
VDD2
D9
VDD3
G7
VDD4
K2
VDD5
K8
VDD6
N1
VDD7
N9
VDD8
R1
VDD9
R9
VDDQ1
A1
VDDQ2
A8
VDDQ3
C1
VDDQ4
C9
VSS1
A9
VSS2
B3
VSS3
E1
VSS4
G8
VSS5
J2
VSS6
J8
VSS7
M1
VSS8
M9
VSS9
P1
VSS10
P9
VSS11
T1
VSS12
T9
VSSQ1
B1
VSSQ2
B9
VSSQ3
D1
VSSQ4
D8
VSSQ5
E2
NC_L1
L1
NC_L9
L9
NC_M7
M7
NC_T7
T7
DQ0
E3
DQ1
F7
DQ2
F2
DQ3
F8
DQ4
H3
DQ5
H8
DQ6
G2
DQ7
H7
A10/AP
L7
A11
R7
A12/BC
N7
LDQS
F3
LDQS
G3
UDQS
C7
UDQS
B7
DQ8
D7
DQ9
C3
DQ10
C8
DQ11
C2
DQ12
A7
DQ13
A2
DQ14
B8
DQ15
A3
VDDQ5
D2
VDDQ6
E9
VDDQ7
F1
VDDQ8
H2
VDDQ9
H9
VSSQ6
E8
VSSQ7
F9
VSSQ8
G1
VSSQ9
G9
A13
T3
NC_J9
J9
NC_J1
J1
CK
J7
CK
K7
CKE
K9
CS
L2
RAS
J3
CAS
K3
WE
L3
RESET
T2
ODT
K1
VREFCA
M8
VREFDQ
H1
ZQ
L8
LDM
E7
UDM
D3
2G_DDR3_SDRAM_128MX16
U4
MT41J128M16HA-15E
2G_DDR3_SDRAM_128MX16
U4
MT41J128M16HA-15E
R170 R170
C88
0.1UF
C88
0.1UF
C103
0.01UF
C103
0.01UF
C104
0.1UF
C104
0.1UF
C73
0.1UF
C73
0.1UF
C115
0.1UF
C115
0.1UF
C94
0.01UF
C94
0.01UF
R8
470
R8
470
R16
240
R16
240
C95
0.1UF
C95
0.1UF
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
BA0
M2
BA1
N8
BA2
M3
VDD1
B2
VDD2
D9
VDD3
G7
VDD4
K2
VDD5
K8
VDD6
N1
VDD7
N9
VDD8
R1
VDD9
R9
VDDQ1
A1
VDDQ2
A8
VDDQ3
C1
VDDQ4
C9
VSS1
A9
VSS2
B3
VSS3
E1
VSS4
G8
VSS5
J2
VSS6
J8
VSS7
M1
VSS8
M9
VSS9
P1
VSS10
P9
VSS11
T1
VSS12
T9
VSSQ1
B1
VSSQ2
B9
VSSQ3
D1
VSSQ4
D8
VSSQ5
E2
NC_L1
L1
NC_L9
L9
NC_M7
M7
NC_T7
T7
DQ0
E3
DQ1
F7
DQ2
F2
DQ3
F8
DQ4
H3
DQ5
H8
DQ6
G2
DQ7
H7
A10/AP
L7
A11
R7
A12/BC
N7
LDQS
F3
LDQS
G3
UDQS
C7
UDQS
B7
DQ8
D7
DQ9
C3
DQ10
C8
DQ11
C2
DQ12
A7
DQ13
A2
DQ14
B8
DQ15
A3
VDDQ5
D2
VDDQ6
E9
VDDQ7
F1
VDDQ8
H2
VDDQ9
H9
VSSQ6
E8
VSSQ7
F9
VSSQ8
G1
VSSQ9
G9
A13
T3
NC_J9
J9
NC_J1
J1
CK
J7
CK
K7
CKE
K9
CS
L2
RAS
J3
CAS
K3
WE
L3
RESET
T2
ODT
K1
VREFCA
M8
VREFDQ
H1
ZQ
L8
LDM
E7
UDM
D3
2G_DDR3_SDRAM_128MX16
U2
MT41J128M16HA-15E
2G_DDR3_SDRAM_128MX16
U2
MT41J128M16HA-15E
C72
0.1UF
C72
0.1UF
C97
0.1UF
C97
0.1UF
C123
0.1UF
C123
0.1UF
C77
0.1UF
C77
0.1UF
C70
0.1UF
C70
0.1UF
C121
0.1UF
C121
0.1UF
R150 R150
C112
0.1UF
C112
0.1UF
C79
10UF
C79
10UF
C124
10UF
C124
10UF
C99
10UF
C99
10UF
C81
0.1UF
C81
0.1UF
C108
0.1UF
C108
0.1UF
C87
0.01UF
C87
0.01UF
C118
0.1UF
C118
0.1UF
C68
0.1UF
C68
0.1UF
C86
0.1UF
C86
0.1UF
R20
240
R20
240
C92
0.01UF
C92
0.01UF
C78
0.01UF
C78
0.01UF
R140 R140
C102
0.1UF
C102
0.1UF
C93
0.1UF
C93
0.1UF
C114
0.1UF
C114
0.1UF