2001 IEEE Verilog标准修订版：硬件描述语言详解
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IEEE 1364-2001 Verilog标准，全称为"IEEE Standard Verilog Hardware Description Language"，是由美国电气与电子工程师协会（IEEE）发布的一项关键的硬件描述语言规范。该标准是对1995年版IEEE 1364的修订版本，旨在提供更加完善和标准化的方法来设计、描述和验证数字电路系统。Verilog是一种广泛应用于电子设计自动化（EDA）领域的高级硬件描述语言，它允许工程师以文本形式描述硬件系统的逻辑结构，包括组合逻辑、时序逻辑、模块化设计、接口描述等。
该标准的主要内容包括但不限于：
1. **语法和语义**：定义了Verilog的编程规则，如数据类型、操作符、流程控制语句、模块化结构（模块、端口声明、参数等）以及信号行为的描述方式。
2. **数据类型和存储器**：支持多种数据类型，如整型、实型、逻辑型，以及不同类型的存储器（寄存器、RAM、ROM等），并规定了它们的使用方法和特性。
3. **设计模块化**：鼓励设计师使用模块化思想，通过函数库和子模块重用代码，提高设计的可维护性和灵活性。
4. **定时分析**：定义了事件驱动的时序模型，允许精确描述信号的时序关系，这对于同步和异步电路设计至关重要。
5. **仿真和验证**：标准提供了模拟和行为仿真工具，用于测试和调试设计，确保其功能正确性。
6. **兼容性和互操作性**：IEEE 1364-2001定义了与其他Verilog版本（如IEEE 1364-1995）的兼容性，以及与硬件描述语言的互操作性。
7. **版权和许可**：强调所有复制和使用本标准必须获得出版商的书面许可，体现了知识产权保护的重要性。
通过阅读和遵循IEEE 1364-2001 Verilog标准，工程师可以确保他们的设计遵循行业最佳实践，提高工作效率，同时也能促进整个电子设计产业的规范化和一致性。对于电子工程学生和从业者来说，掌握这个标准是进行高级硬件设计的关键。如果你是TIANJIN UNIVERSITY的用户，并于2020年7月19日下载了这份标准，那么在使用过程中请注意相关限制条件。
Copyright © 2001 IEEE. All rights reserved. xv
15.3.4 $width ....................................................................................................................... 255
15.3.5 $period ...................................................................................................................... 256
15.3.6 $nochange ................................................................................................................. 257
15.4 Edge-control specifiers .......................................................................................................... 258
15.5 Notifiers: user-defined responses to timing violations .......................................................... 260
15.5.1 Requirements for accurate simulation ...................................................................... 262
15.5.2 Conditions in negative timing checks....................................................................... 264
15.5.3 Notifiers in negative timing checks .......................................................................... 266
15.5.4 Option behavior ........................................................................................................ 266
15.6 Enabling timing checks with conditioned events................................................................... 266
15.7 Vector signals in timing checks............................................................................................. 267
15.8 Negative timing checks.......................................................................................................... 268
16. Backannotation using the Standard Delay Format (SDF)................................................................ 270
16.1 The SDF annotator................................................................................................................. 270
16.2 Mapping of SDF constructs to Verilog.................................................................................. 270
16.2.1 Mapping of SDF delay constructs to Verilog declarations....................................... 270
16.2.2 Mapping of SDF timing check constructs to Verilog............................................... 272
16.2.3 SDF annotation of specparams ................................................................................. 273
16.2.4 SDF annotation of interconnect delays..................................................................... 274
16.3 Multiple annotations .............................................................................................................. 275
16.4 Multiple SDF files ................................................................................................................. 276
16.5 Pulse limit annotation ............................................................................................................ 276
16.6 SDF to Verilog delay value mapping..................................................................................... 277
17. System tasks and functions.............................................................................................................. 278
17.1 Display system tasks.............................................................................................................. 278
17.1.1 The display and write tasks....................................................................................... 279
17.1.2 Strobed monitoring ................................................................................................... 286
17.1.3 Continuous monitoring ............................................................................................. 287
17.2 File input-output system tasks and functions......................................................................... 287
17.2.1 Opening and closing files.......................................................................................... 287
17.2.2 File output system tasks............................................................................................ 289
17.2.3 Formatting data to a string........................................................................................ 290
17.2.4 Reading data from a file............................................................................................ 291
17.2.5 File positioning ......................................................................................................... 295
17.2.6 Flushing output ......................................................................................................... 295
17.2.7 I/O error status .......................................................................................................... 295
17.2.8 Loading memory data from a file ............................................................................. 296
17.2.9 Loading timing data from an SDF file...................................................................... 297
17.3 Timescale system tasks.......................................................................................................... 298
17.3.1 $printtimescale.......................................................................................................... 298
17.3.2 $timeformat............................................................................................................... 299
17.4 Simulation control system tasks ............................................................................................ 302
17.4.1 $finish ....................................................................................................................... 302
17.4.2 $stop.......................................................................................................................... 302
17.5 PLA modeling system tasks................................................................................................... 303
17.5.1 Array types................................................................................................................ 303
17.5.2 Array logic types....................................................................................................... 304
17.5.3 Logic array personality declaration and loading....................................................... 304
17.5.4 Logic array personality formats................................................................................ 304
Authorized licensed use limited to: TIANJIN UNIVERSITY. Downloaded on July 19,2020 at 03:19:24 UTC from IEEE Xplore. Restrictions apply.
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