2010年《计算机组织与性能设计》英文版详解

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《计算机组成与体系结构-性能设计》(2010年第八版)是由William Stallings所著的一本经典著作，该书专注于计算机系统的内部构造和设计，特别强调性能优化。作为一部英文教材，它涵盖了计算机科学的基础知识，包括处理器、存储器、输入/输出系统、指令集架构以及计算机网络等方面，旨在帮助读者理解和掌握如何通过深入理解这些核心概念来提升系统的性能。本书的章节可能涉及以下知识点： 1. **计算机组织**：这部分会介绍计算机硬件的基本组成部分，如中央处理器(CPU)、内存、主板、总线等，阐述它们如何协同工作，形成计算机的执行环境。 2. **体系结构设计**：这部分将探讨不同类型的体系结构，如冯诺依曼架构、哈佛架构、RISC和CISC（复杂指令集计算机）的区别，以及现代多核和并行处理技术。 3. **性能指标**：性能设计的核心内容，可能包括吞吐量、时延、带宽、缓存优化、指令级并行性、能量效率等关键指标的计算和测量。 4. **流水线和超线程技术**：如何通过流水线设计提高处理器速度，以及超线程技术如何扩展单个核心的能力，以实现更高的性能。 5. **存储系统优化**：从主存到外存的层次结构，包括高速缓存的设计策略，以及磁盘和网络I/O性能的提升方法。 6. **并发和并行处理**：讲解线程调度、死锁、同步与互斥等并发控制技术，以及分布式系统中的性能优化。 7. **虚拟化与云计算**：随着云计算的发展，虚拟化技术在性能设计中的作用，以及如何通过资源池化和负载均衡提高整体性能。 8. **基准测试和性能分析**：介绍如何评估和优化系统性能，包括基准测试工具的使用和性能瓶颈的识别方法。 9. **未来趋势**：书中可能还关注当前和未来的计算技术发展，如量子计算、人工智能和边缘计算对性能设计的影响。《计算机组成与体系结构-性能设计英文(2010)》是一本既适合专业学生学习，也供研究人员参考的重要资源，提供了丰富的理论知识和实践指导，帮助读者在不断发展的IT领域中实现高性能计算机系统的设计与优化。

PREFACE xv

For the professional interested in this field, the book serves as a basic reference volume

and is suitable for self-study.

INSTRUCTIONAL SUPPORT MATERIALS

To support instructors, the following materials are provided:

• Solutions manual: Solutions to end-of-chapter Review Questions and Problems

• Projects manual: Suggested project assignments for all of the project categories

listed below

• PowerPoint slides: A set of slides covering all chapters, suitable for use in lecturing

• PDF files: Reproductions of all figures and tables from the book

• Test bank: Includes true/false, multiple choice, and fill-in-the-blanks questions

and answers

All of these support materials are available at the Instructor Resource Center (IRC)

for this textbook.To gain access to the IRC, please contact your local Prentice Hall sales rep-

resentative via prenhall.com/replocator or call Prentice Hall Faculty Services at 1-800-526-

0485. You can also locate the IRC through http://www.pearsonhighered.com/stallings.

INTERNET SERVICES FOR INSTRUCTORS AND STUDENTS

There is a Web site for this book that provides support for students and instructors. The site

includes links to other relevant sites and a set of useful documents. See the section, “Web

Site for Computer Organization and Architecture,” preceding this Preface, for more infor-

mation. The Web page is at williamstallings.com/COA/COA8e.html.

New to this edition is a set of homework problems with solutions publicly available at

this Web site. Students can enhance their understanding of the material by working out the

solutions to these problems and then checking their answers.

An Internet mailing list has been set up so that instructors using this book can ex-

change information, suggestions, and questions with each other and with the author.As soon

as typos or other errors are discovered, an errata list for this book will be available at

WilliamStallings.com. Finally, I maintain the Computer Science Student Resource Site at

WilliamStallings.com/StudentSupport.html.

PROJECTS AND OTHER STUDENT EXERCISES

For many instructors, an important component of a computer organization and architecture

course is a project or set of projects by which the student gets hands-on experience to rein-

force concepts from the text. This book provides an unparalleled degree of support for in-

cluding a projects component in the course. The instructor’s support materials available

through Prentice Hall not only includes guidance on how to assign and structure the projects

but also includes a set of user’s manuals for various project types plus specific assignments,

all written especially for this book. Instructors can assign work in the following areas:

• Interactive simulation assignments: Described subsequently.

• Research projects: A series of research assignments that instruct the student to re-

search a particular topic on the Internet and write a report.

xvi PREFACE

• Simulation projects: The IRC provides support for the use of the two simulation pack-

ages: SimpleScalar can be used to explore computer organization and architecture

design issues. SMPCache provides a powerful educational tool for examining cache

design issues for symmetric multiprocessors.

• Assembly language projects: A simplified assembly language, CodeBlue, is used and

assignments based on the popular Core Wars concept are provided.

• Reading/report assignments: A list of papers in the literature, one or more for each

chapter, that can be assigned for the student to read and then write a short report.

• Writing assignments: A list of writing assignments to facilitate learning the material.

• Test bank: Includes T/F, multiple choice, and fill-in-the-blanks questions and answers.

This diverse set of projects and other student exercises enables the instructor to use the

book as one component in a rich and varied learning experience and to tailor a course plan to

meet the specific needs of the instructor and students. See Appendix A in this book for details.

INTERACTIVE SIMULATIONS

New to this edition is the incorporation of interactive simulations. These simulations provide a

powerful tool for understanding the complex design features of a modern computer system. A

total of 20 interactive simulations are used to illustrate key functions and algorithms in com-

puter organization and architecture design. At the relevant point in the book, an icon indicates

that a relevant interactive simulation is available online for student use. Because the animations

enable the user to set initial conditions, they can serve as the basis for student assignments. The

instructor’s supplement includes a set of assignments, one for each of the animations. Each

assignment includes a several specific problems that can be assigned to students.

WHAT’S NEW IN THE EIGHTH EDITION

In the four years since the seventh edition of this book was published, the field has seen

continued innovations and improvements. In this new edition, I try to capture these

changes while maintaining a broad and comprehensive coverage of the entire field. To

begin this process of revision, the seventh edition of this book was extensively reviewed by

a number of professors who teach the subject and by professionals working in the field.

The result is that, in many places, the narrative has been clarified and tightened, and illus-

trations have been improved. Also, a number of new “field-tested” homework problems

have been added.

Beyond these refinements to improve pedagogy and user friendliness, there have been

substantive changes throughout the book. Roughly the same chapter organization has been

retained, but much of the material has been revised and new material has been added. The

most noteworthy changes are as follows:

• Interactive simulation: Simulation provides a powerful tool for understanding the

complex mechanisms of a modern processor.The eighth edition incorporates 20 sepa-

rate interactive, Web-based simulation tools covering such areas as cache memory,

main memory, I/O, branch prediction, instruction pipelining, and vector processing. At

appropriate places in the book, the simulators are highlighted so that the student can

invoke the simulation at the proper point in studying the book.

PREFACE xvii

• Embedded processors: The eighth edition now includes coverage of embedded proces-

sors and the unique design issues they present. The ARM architecture is used as a

case study.

• Multicore processors: The eighth edition now includes coverage of what has become

the most prevalent new development in computer architecture: the use of multiple

processors on a single chip. Chapter 18 is devoted to this topic.

• Cache memory: Chapter 4, which is devoted to cache memory, has been extensively

revised, updated, and expanded to provide broader technical coverage and im-

proved pedagogy through the use of numerous figures, as well as interactive simula-

tion tools.

• Performance assessment: Chapter 2 includes a significantly expanded discussion of

performance assessment, including a new discussion of benchmarks and an analysis of

Amdahl’s law.

• Assembly language: A new appendix has been added that covers assembly language

and assemblers.

• Programmable logic devices: The discussion of PLDs in Chapter 20 on digital logic has

been expanded to include an introduction to field-programmable gate arrays

(FPGAs).

• DDR SDRAM: DDR has become the dominant main memory technology in desktops

and servers, particularly DDR2 and DDR3. DDR technology is covered in Chapter 5,

with additional details in Appendix K.

• Linear tape open (LTO): LTO has become the best selling “super tape” format and is

widely used with small and large computer systems, especially for backup, LTO is cov-

ered in Chapter 6, with additional details in Appendix J.

With each new edition it is a struggle to maintain a reasonable page count while adding

new material. In part this objective is realized by eliminating obsolete material and tighten-

ing the narrative. For this edition, chapters and appendices that are of less general interest

have been moved online, as individual PDF files. This has allowed an expansion of material

without the corresponding increase in size and price.

ACKNOWLEDGEMENTS

This new edition has benefited from review by a number of people, who gave generously of

their time and expertise. The following people reviewed all or a large part of the manuscript:

Azad Azadmanesh (University of Nebraska–Omaha); Henry Casanova (University of Hawaii);

Marge Coahran (Grinnell College); Andree Jacobsen (University of New Mexico); Kurtis

Kredo (University of California—Davis); Jiang Li (Austin Peay State University); Rachid

Manseur (SUNY, Oswego); John Masiyowski (George Mason University); Fuad Muztaba

(Winston-Salem State University); Bill Sverdlik (Eastern Michigan University); and Xiaobo

Zhou (University of Colorado Colorado Springs).

Thanks also to the people who provided detailed technical reviews of a single chapter:

Tim Mensch, Balbir Singh, Michael Spratte (Hewlett-Packard), François-Xavier Peretmere,

John Levine, Jeff Kenton, Glen Herrmannsfeldt, Robert Thorpe, Grzegorz Mazur (Institute

of Computer Science, Warsaw University of Technology), Ian Ameline, Terje Mathisen, Ed-

ward Brekelbaum (Varilog Research Inc), Paul DeMone, and Mikael Tillenius. I would also

like to thank Jon Marsh of ARM Limited for the review of the material on ARM.

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