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PREFACE xvii
• Embedded processors: The eighth edition now includes coverage of embedded proces-
sors and the unique design issues they present. The ARM architecture is used as a
case study.
• Multicore processors: The eighth edition now includes coverage of what has become
the most prevalent new development in computer architecture: the use of multiple
processors on a single chip. Chapter 18 is devoted to this topic.
• Cache memory: Chapter 4, which is devoted to cache memory, has been extensively
revised, updated, and expanded to provide broader technical coverage and im-
proved pedagogy through the use of numerous figures, as well as interactive simula-
tion tools.
• Performance assessment: Chapter 2 includes a significantly expanded discussion of
performance assessment, including a new discussion of benchmarks and an analysis of
Amdahl’s law.
• Assembly language: A new appendix has been added that covers assembly language
and assemblers.
• Programmable logic devices: The discussion of PLDs in Chapter 20 on digital logic has
been expanded to include an introduction to field-programmable gate arrays
(FPGAs).
• DDR SDRAM: DDR has become the dominant main memory technology in desktops
and servers, particularly DDR2 and DDR3. DDR technology is covered in Chapter 5,
with additional details in Appendix K.
• Linear tape open (LTO): LTO has become the best selling “super tape” format and is
widely used with small and large computer systems, especially for backup, LTO is cov-
ered in Chapter 6, with additional details in Appendix J.
With each new edition it is a struggle to maintain a reasonable page count while adding
new material. In part this objective is realized by eliminating obsolete material and tighten-
ing the narrative. For this edition, chapters and appendices that are of less general interest
have been moved online, as individual PDF files. This has allowed an expansion of material
without the corresponding increase in size and price.
ACKNOWLEDGEMENTS
This new edition has benefited from review by a number of people, who gave generously of
their time and expertise. The following people reviewed all or a large part of the manuscript:
Azad Azadmanesh (University of Nebraska–Omaha); Henry Casanova (University of Hawaii);
Marge Coahran (Grinnell College); Andree Jacobsen (University of New Mexico); Kurtis
Kredo (University of California—Davis); Jiang Li (Austin Peay State University); Rachid
Manseur (SUNY, Oswego); John Masiyowski (George Mason University); Fuad Muztaba
(Winston-Salem State University); Bill Sverdlik (Eastern Michigan University); and Xiaobo
Zhou (University of Colorado Colorado Springs).
Thanks also to the people who provided detailed technical reviews of a single chapter:
Tim Mensch, Balbir Singh, Michael Spratte (Hewlett-Packard), François-Xavier Peretmere,
John Levine, Jeff Kenton, Glen Herrmannsfeldt, Robert Thorpe, Grzegorz Mazur (Institute
of Computer Science, Warsaw University of Technology), Ian Ameline, Terje Mathisen, Ed-
ward Brekelbaum (Varilog Research Inc), Paul DeMone, and Mikael Tillenius. I would also
like to thank Jon Marsh of ARM Limited for the review of the material on ARM.