计算机组成与体系结构设计详解：第七/八版课后答案资源

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《计算机组成与体系结构：设计性能第七版》是由William Stallings所著的一本经典教材，该书主要探讨计算机系统的设计原则，尤其是如何优化系统的性能。这本书在第七版和第八版中保持了内容的稳定性，因此，无论是哪个版本的学生，都可以找到相关的学习资料。本书的核心知识点包括以下几个方面： 1. **计算机组成原理**：涵盖了计算机硬件的基本构成，如处理器（CPU）、内存、输入输出设备等，以及它们之间的相互作用。学习者会理解指令集架构（ISA），数据表示和存储体系结构，以及处理器内部的流水线设计。 2. **体系结构设计**：重点在于阐述如何设计高效的计算机系统，包括处理器设计、内存管理、虚拟存储器、并发控制和同步机制，以及错误检测和恢复策略。 3. **性能优化**：讨论如何通过硬件和软件的协同工作来提高系统的整体性能，包括处理器频率、指令级并行性、缓存优化和内存访问效率等。 4. **问题解答与习题集**：书中附有大量的复习问题和作业题目，课后答案网（www.hackshp.cn）提供了这些题目及其答案，对于学习者来说是重要的参考资料，可以帮助理解和巩固理论知识，解决学习过程中的疑难问题。 5. **版权声明**：作者强调所有版权权益，禁止未经许可任何形式的复制或在网上发布文档内容，尊重知识产权，鼓励读者在发现错误时通过电子邮件向作者反馈。课后答案网是一个专门为学生提供服务的平台，它不仅提供《计算机组织与体系结构》第七版的课后答案，还链接了视频教程网（www.efanjy.com）和PPT课件网（www.ppthouse.com），为学习者提供了多元化的学习资源。对于那些希望自主学习或需要解决作业难题的学生来说，这个网站是一个非常实用的学习工具。《计算机组成与体系结构课后答案》是一本深入浅出的教材，配合在线资源，为学生系统学习计算机体系结构提供了丰富的支持，同时强调了学术诚信和尊重知识产权的重要性。

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cache control logic. Temporal locality is exploited by keeping recently used

instruction and data values in cache memory and by exploiting a cache hierarchy.

NSWERS TO

ROBLEMS

4.1 The cache is divided into 16 sets of 4 lines each. Therefore, 4 bits are needed to

identify the set number. Main memory consists of 4K = 2

blocks. Therefore, the set

plus tag lengths must be 12 bits and therefore the tag length is 8 bits. Each block

contains 128 words. Therefore, 7 bits are needed to specify the word.

TAG

SET

WORD

Main memory address =

4.2 There are a total of 8 kbytes/16 bytes = 512 lines in the cache. Thus the cache

consists of 256 sets of 2 lines each. Therefore 8 bits are needed to identify the set

number. For the 64-Mbyte main memory, a 26-bit address is needed. Main memory

consists of 64-Mbyte/16 bytes = 2

blocks. Therefore, the set plus tag lengths must

be 22 bits, so the tag length is 14 bits and the word field length is 4 bits.

TAG

SET

WORD

Main memory address =

4.3

Address

111111

666666

BBBBBB

a. Tag/Line/Word

11/444/1

66/1999/2

BB/2EEE/3

b. Tag /Word

44444/1

199999/2

2EEEEE/3

c. Tag/Set/Word

22/444/1

CC/1999/2

177/EEE/3

4.4 a. Address length: 24; number of addressable units: 2

; block size: 4; number of

blocks in main memory: 2

; number of lines in cache: 2

; size of tag: 8.

b. Address length: 24; number of addressable units: 2

; block size: 4; number of

blocks in main memory: 2

; number of lines in cache: 4000 hex; size of tag: 22.

c. Address length: 24; number of addressable units: 2

; block size: 4; number of

blocks in main memory: 2

; number of lines in set: 2; number of sets: 2

;

number of lines in cache: 2

; size of tag: 9.

4.5 Block frame size = 16 bytes = 4 doublewords

Number of block frames in cache =

16 KBytes

16 Bytes

= 1024

Number of sets =

Number of block frames

Associativity

1024

= 256 sets

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4.9 a. The bits are set according to the following rules with each access to the set:

1. If the access is to L0 or L1, B0 ← 1.

2. If the access is to L0, B1 ← 1.

3. If the access is to L1, B1 ← 0.

4. If the access is to L2 or L3, B0 ← 0.

5. If the access is to L2, B2 ← 1.

6. If the access is to L3, B2 ← 0.

The replacement algorithm works as follows (Figure 4.15): When a line must be

replaced, the cache will first determine whether the most recent use was from

L0 and L1 or L2 and L3. Then the cache will determine which of the pair of

blocks was least recently used and mark it for replacement. When the cache is

initialized or flushed all 128 sets of three LRU bits are set to zero.

b. The 80486 divides the four lines in a set into two pairs (L0, L1 and L2, L3). Bit

B0 is used to select the pair that has been least-recently used. Within each pair,

one bit is used to determine which member of the pair was least-recently used.

However, the ultimate selection only approximates LRU. Consider the case in

which the order of use was: L0, L2, L3, L1. The least-recently used pair is (L2,

L3) and the least-recently used member of that pair is L2, which is selected for

replacement. However, the least-recently used line of all is L0. Depending on

the access history, the algorithm will always pick the least-recently used entry

or the second least-recently used entry.

c. The most straightforward way to implement true LRU for a four-line set is to

associate a two bit counter with each line. When an access occurs, the counter

for that block is set to 0; all counters with values lower than the original value

for the accessed block are incremented by 1. When a miss occurs and the set is

not full, a new block is brought in, its counter is set to 0 and all other counters

are incremented by 1. When a miss occurs and the set is full, the block with

counter value 3 is replaced; its counter is set to 0 and all other counters are

incremented by 1. This approach requires a total of 8 bits.

In general, for a set of N blocks, the above approach requires 2N bits. A

more efficient scheme can be designed which requires only N(N–1)/2 bits. The

scheme operates as follows. Consider a matrix R with N rows and N columns,

and take the upper-right triangular portion of the matrix, not counting the

diagonal. For N = 4, we have the following layout:

R(1,2)

R(1,3)

R(1,4)

R(2,3)

R(2,4)

R(3,4)

When line I is referenced, row I of R(I,J) is set to 1, and column I of R(J,I) is set

to 0. The LRU block is the one for which the row is entirely equal to 0 (for those

bits in the row; the row may be empty) and for which the column is entirely 1

(for all the bits in the column; the column may be empty). As can be seen for N

= 4, a total of 6 bits are required.

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