KSZ9477S: 10/100/1000 Ethernet with SGMII & RGMII Interface

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"KSZ9477S是一款由Microchip公司生产的高性能以太网解决方案，支持10/100/1000Mbps速率，具有集成的PHY和多种接口选项，适用于工业自动化和实时网络应用。" 本文将详细讨论KSZ9477S的主要特性、功能和应用领域。 KSZ9477S是Microchip Technology Inc.推出的一款高度集成的以太网交换芯片，具备10/100/1000 Mbps的传输速度，可提供灵活的接口选择，以适应不同网络环境的需求。该芯片的核心特性包括： 1. **双端口MAC设计**：KSZ9477S包含一个端口支持10/100/1000 Ethernet MAC与Synchronous Gigabit Media Independent Interface (SGMII)接口，另一个端口则支持可配置的Reduced Gigabit Media Independent Interface (RGMII)/Media Independent Interface (MII)/Reduced MII (RMII)接口。这些接口提供了灵活的连接选择，便于与各种网络设备对接。 2. **时间同步技术**：支持EtherSynch®功能，完全兼容IEEE 1588v2 Precision Time Protocol (PTP)，确保在网络中实现精确的时间同步，这对于需要严格时间对齐的应用（如音频视频桥接和电力系统自动化）至关重要。 3. **音频视频桥接**：遵循IEEE 802.1AS标准，提供高质量的Qav Audio Video Bridging (AVB)服务，优化了音视频数据在网络中的传输。 4. **安全控制**：支持IEEE 802.1X访问控制，增强了网络安全，允许仅授权设备接入网络。 5. **集成PHY**：五个端口集成了10/100/1000BASE-T PHY收发器，且可以选择Quiet-WIRE®电磁兼容（EMC）过滤，减少电磁干扰，提高网络稳定性。 6. **非阻塞交换架构**：采用非阻塞的线速以太网交换结构，确保所有端口在满负荷运行时仍能保持高效无损的数据传输。 7. **高级转发和过滤**：提供完整的转发和过滤控制，包括Access Control List (ACL)过滤，可精细管理网络流量和安全策略。 8. **VLAN和QoS支持**：支持全VLAN功能和服务质量（QoS）策略，可以进行优先级划分，确保关键数据的优先传输。 9. **节能特性**： EtherGreen™电源管理功能支持低功耗待机模式，有助于降低整体能耗。 10. **管理接口**：提供SPI、I2C、MIIM和通过任何端口的带内管理接口，便于设备配置和监控。 11. **工业级温度范围**：能够适应广泛的温度范围，适用于严苛的工业环境。 12. **封装形式**：采用128引脚TQFP-EP封装（14x14mm），符合RoHS标准。 **目标应用领域**： - 工业以太网：如Profinet、MODBUS、Ethernet/IP等协议的网络。 - 实时以太网网络：对于需要快速响应和时间敏感通信的系统。 - IEC 61850网络：在电力系统自动化中广泛应用。 - 工业控制/自动化开关：用于构建可靠的工业网络基础设施。 - 网络化测量和控制：在自动化和监测系统中提供稳定的数据传输。 KSZ9477S凭借其丰富的功能和适应性，成为了工业自动化、实时网络和电力系统自动化等领域的理想选择，为高效、安全的网络通信提供了强大支持。

KSZ9477S

DS00002392A-page 16  2017 Microchip Technology Inc.

Port 4

LED Indicator 0

LED4_0 IPU/O8 Port 4 LED Indicator 0.

Active low output sinks current to light an external LED.

Note: This pin also provides configuration strap func-

tions during hardware/software resets. Refer to

Section 3.2.1, "Configuration Straps" for addi-

tional information.

Port 4

LED Indicator 1

LED4_1 IPU/O8 Port 4 LED Indicator 1.

Active low output sinks current to light an external LED.

Note: This pin also provides configuration strap func-

tions during hardware/software resets. Refer to

Section 3.2.1, "Configuration Straps" for addi-

tional information.

Port 5

LED Indicator 0

LED5_0 IPU/O8 Port 5 LED Indicator 0.

Active low output sinks current to light an external LED.

Port 5

LED Indicator 1

LED5_1 IPU/O8 Port 5 LED Indicator 1.

Active low output sinks current to light an external LED.

Note: This pin also provides configuration strap func-

tions during hardware/software resets. Refer to

Section 3.2.1, "Configuration Straps" for addi-

tional information.

Miscellaneous Pins

Interrupt INTRP_N OPU Active low, open-drain interrupt.

Note: This pin requires an external pull-up resistor.

Power

Management

Event

PME_N O8 Power Management Event.

This output signal indicates that an energy detect event has

occurred. It is intended to wake up the system from a low

power mode.

Note: The assertion polarity is programmable (default

active low). An external pull-up resistor is

required for active-low operation; an external

pull-down resistor is required for active-high

operation.

System Reset RESET_N IPU Active low system reset.

The device must be reset either during or after power-on.

An RC circuit is suggested for power-on reset.

Crystal Clock /

Oscillator Input

XI ICLK Crystal clock / oscillator input.

When using a 25MHz crystal, this input is connected to one

lead of the crystal. When using an oscillator, this pin is the

input from the oscillator. The crystal oscillator should have a

tolerance of ±50ppm.

Crystal Clock

Output

XO OCLK Crystal clock / oscillator output.

When using a 25MHz crystal, this output is connected to

one lead of the crystal. When using an oscillator, this pin is

left unconnected.

25/125MHz

Reference

Clock Output

SYNCLKO IPU/O24 25/125MHz reference clock output, derived from the crystal

input or the recovered clock of any PHY. This signal may be

used for Synchronous Ethernet.

TABLE 3-2: PIN DESCRIPTIONS (CONTINUED)

Name Symbol

Buffer

Type

Description

KSZ9477S

DS00002392A-page 18  2017 Microchip Technology Inc.

3.2.1 CONFIGURATION STRAPS

The KSZ9477S utilizes configuration strap pins to configure the device for different modes. While RESET_N is low,

these pins are hi-Z. Pull-up/down resistors are used to create high or low states on these pins, which are internally sam-

pled at the rising edge of RESET_N. All of these pins have a weak internal pull-up or pull-down resistor which provides

a default level for strapping. To strap an LED pin low, use a 750Ω to 1kΩ external pull-down resistor. To strap a non-LED

pin high, use an external 1kΩ to 10kΩ pull-up resistor to VDDIO. Once RESET_N is high, all of these pins become driven

outputs.

Because the internal pull-up/down resistors are not strong, consideration must be given to any other pull-up/down resis-

tors which may reside on the board or inside a device connected to these pins.

When an LED pin is directly driving an LED, the effect of the LED and LED load resistor on the strapping level must be

considered. This is the reason for using a small value resistor to pull an LED pin low. This is especially true when an

LED is powered from a voltage that is higher than VDDIO.

The configuration strap pins and their associated functions are detailed in Ta b le 3- 3 .

TABLE 3-3: CONFIGURATION STRAP DESCRIPTIONS

Configuration

Strap Pin

Description

LED1_0 Quiet-WIRE Filtering Enable

0: Quiet-WIRE filtering enabled

1: Quiet-WIRE filtering disabled (Default)

LED1_1 Flow Control (All Ports)

0: Flow control disabled

1: Flow control enabled (Default)

LED2_1 Link-up Mode (All PHYs)

0: Fast Link-up: Auto-negotiation and auto MDI/MDI-X are disabled

1: Normal Link-up: Auto-negotiation and auto MDI/MDI-X are enabled (Default)

Note: Since Fast Link-up disables auto-negotiation and auto-crossover, it is suitable only

for specialized applications.

LED2_0, LED4_0 When LED2_1 = 1 at strap-in (Normal Link-up):

[LED2_0, LED4_0]: Auto-Negotiation Enable (All PHYs) / NAND Tree Test Mode

00: Reserved

01: Auto-negotiation disabled

10: NAND Tree test mode

11: Auto-negotiation enabled (Default)

When LED2_1 = 0 at strap-in (Fast Link-up; All PHYs Full-Duplex):

LED2_0: 1000BASE-T Master/Slave Mode, 10/100BASE-T MDI/MDI-X Mode (All PHYs)

0: 1000BASE-T: Slave Mode

10/100BASE-T: MDI-X

1: 1000BASE-T: Master Mode (Default)

10/100BASE-T: MDI (Default)

LED4_0: PHY Speed Select (All PHYs)

0: 1000BASE-T

1: 100BASE-TX (Default)

LED4_1, LED3_1 [LED4_1, LED3_1]: Management Interface Mode

00: MIIM (MDIO)

01: I

1x: SPI (Default)

LED5_1 Switch Enable at Startup

0: Start Switch is disabled. The switch will not forward packets until the Start Switch bit is set

in the Switch Operation Register.

1: Start Switch is enabled. The switch will forward packets immediately after reset. (Default)

KSZ9477S

DS00002392A-page 20  2017 Microchip Technology Inc.

4.0 FUNCTIONAL DESCRIPTION

This section provides functional descriptions for the following:

• Physical Layer Transceiver (PHY)

• LEDs

• Media Access Controller (MAC)

• Switch

• Ring Redundancy

• IEEE 1588 Precision Time Protocol

• Audio Video Bridging and Time Sensitive Networks

• NAND Tree Support

• Clocking

• Power

• Power Management

• Management Interface

• In-Band Management

• MAC Interface (Ports 6 and 7)

4.1 Physical Layer Transceiver (PHY)

Ports 1 through 5 include completely integrated triple-speed (10BASE-Te, 100BASE-TX, 1000BASE-T) Ethernet phys-

ical layer transceivers for transmission and reception of data over standard four-pair unshielded twisted pair (UTP), CAT-

5 or better Ethernet cable.

The device reduces board cost and simplifies board layout by using on-chip termination resistors for the four differential

pairs, eliminating the need for external termination resistors. The internal chip termination and biasing provides signifi-

cant power savings when compared with using external biasing and termination resistors.

The device can automatically detect and correct for differential pair misplacements and polarity reversals, and correct

for propagation delay differences between the four differential pairs, as specified in the IEEE 802.3 standard for

1000BASE-T operation.

4.1.1 1000BASE-T TRANSCEIVER

The 1000BASE-T transceiver is based on a mixed-signal/digital signal processing (DSP) architecture, which includes

the analog front-end, digital channel equalizers, trellis encoders/decoders, echo cancelers, cross-talk cancelers, a pre-

cision clock recovery scheme, and power-efficient line drivers.

4.1.1.1 Analog Echo Cancellation Circuit

In 1000BASE-T mode, the analog echo cancellation circuit helps to reduce the near-end echo. This analog hybrid circuit

relieves the burden of the ADC and the adaptive equalizer. This circuit is disabled in 10BASE-Te/100BASE-TX mode.

4.1.1.2 Automatic Gain Control (AGC)

In 1000BASE-T mode, the automatic gain control circuit provides initial gain adjustment to boost up the signal level. This

pre-conditioning circuit is used to improve the signal-to-noise ratio of the receive signal.

4.1.1.3 Analog-to-Digital Converter (ADC)

In 1000BASE-T mode, the analog-to-digital converter digitizes the incoming signal. ADC performance is essential to the

overall performance of the transceiver. This circuit is disabled in 10BASE-Te/100BASE-TX mode.

4.1.1.4 Timing Recovery Circuit

In 1000BASE-T mode, the mixed signal clock recovery circuit, together with the digital phase locked loop (PLL), is used

to recover and track the incoming timing information from the received data. The digital PLL has very low long-term jitter

to maximize the signal-to-noise ratio of the receive signal.

The 1000BASE-T slave PHY must transmit the exact receive clock frequency recovered from the received data back to

the 1000BASE-T master PHY. Otherwise, the master and slave will not be synchronized after long transmission. This

also helps to facilitate echo cancellation and NEXT removal.

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