飞思卡尔i.MX6DQ/AEC汽车与信息娱乐处理器技术详解

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"IMX6DQ是飞思卡尔（现为恩智浦半导体）的一款处理器，主要用于汽车电子和信息娱乐系统，具备高性能多媒体处理能力和高度的功能集成。" 本文档是针对Freescale Semiconductor IMX6DQ系列处理器的技术数据手册，修订版本为Rev.4，发布日期为2015年7月。该系列芯片采用FCPBGA封装，尺寸为21x21毫米，引脚间距为0.8毫米。订购信息中列出了几种不同的型号，如MCIMX6QxAxxxxC和MCIMX6QxAxxxxD代表i.MX6 Quad系列，而MCIMX6DxAxxxxC和MCIMX6DxAxxxxD则代表i.MX6 Dual系列。 i.MX6 Dual和i.MX6 Quad处理器是飞思卡尔在多媒体应用处理器领域的最新成果，它们旨在满足汽车信息娱乐、远程信息处理、人机交互（HMI）以及基于显示的仪表集群市场的需求。这两款处理器均搭载了飞思卡尔先进的四核ARM Cortex-A9核心，运行速度可达1GHz。这样的配置提供了强大的计算性能。处理器内置2D和3D图形处理器，支持3D 1080p视频处理，集成了电源管理功能。此外，它们提供了一个64位的DDR3/LVDDR3/LPDDR2-1066内存接口，确保了高速的数据传输和高效的系统运行。这些特性使得i.MX6DQ系列处理器适用于需要高清晰度显示、复杂图形处理和高效能计算的汽车电子应用，如车载信息娱乐系统、导航系统和高级驾驶辅助系统（ADAS）。通过集成的电源管理模块，它们还能实现低功耗运行，这对于车载设备来说至关重要，因为它直接影响到电池寿命和系统的能源效率。 IMX6DQ系列处理器是飞思卡尔针对汽车行业的创新解决方案，通过高度集成的硬件和强大的处理能力，为汽车电子市场带来了前沿的性能表现和功能特性。

i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 4, 07/2015

16 Freescale Semiconductor Inc.

Modules List

SSI-1

SSI-2

SSI-3

I2S/SSI/AC97

Interface

Connectivity

Peripherals

The SSI is a full-duplex synchronous interface, which is used on the

processor to provide connectivity with off-chip audio peripherals. The SSI

supports a wide variety of protocols (SSI normal, SSI network, I2S, and

AC-97), bit depths (up to 24 bits per word), and clock / frame sync options.

The SSI has two pairs of 8x24 FIFOs and hardware support for an

external DMA controller to minimize its impact on system performance.

The second pair of FIFOs provides hardware interleaving of a second

audio stream that reduces CPU overhead in use cases where two time

slots are being used simultaneously.

TEMPMON Temperature Monitor System

Control

Peripherals

The temperature monitor/sensor IP module for detecting high temperature

conditions. The temperature read out does not reflect case or ambient

temperature. It reflects the temperature in proximity of the sensor location

on the die. Temperature distribution may not be uniformly distributed;

therefore, the read out value may not be the reflection of the temperature

value for the entire die.

TZASC Trust-Zone Address

Space Controller

Security The TZASC (TZC-380 by ARM) provides security address region control

functions required for intended application. It is used on the path to the

DRAM controller.

UART-1

UART-2

UART-3

UART-4

UART-5

UART Interface Connectivity

Peripherals

Each of the UARTv2 modules support the following serial data

transmit/receive protocols and configurations:

• 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd

or none)

• Programmable baud rates up to 5 MHz

• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud

• IrDA 1.0 support (up to SIR speed of 115200 bps)

• Option to operate as 8-pins full UART, DCE, or DTE

USBOH3A USB 2.0 High Speed

OTG and 3x HS

Hosts

Connectivity

Peripherals

USBOH3 contains:

• One high-speed OTG module with integrated HS USB PHY

• One high-speed Host module with integrated HS USB PHY

• Two identical high-speed Host modules connected to HSIC USB ports.

Table 2. i.MX 6Dual/6Quad Modules List (continued)

Block

Mnemonic

Block Name Subsystem Brief Description

Modules List

i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 4, 07/2015

Freescale Semiconductor Inc. 17

uSDHC-1

uSDHC-2

uSDHC-4

SD/MMC and SDXC

Enhanced

Multi-Media Card /

Secure Digital Host

Controller

Connectivity

Peripherals

i.MX 6Dual/6Quad specific SoC characteristics:

All four MMC/SD/SDIO controller IPs are identical and are based on the

uSDHC IP. They are:

• Conforms to the SD Host Controller Standard Specification version 3.0

• Fully compliant with MMC command/response sets and Physical Layer

as defined in the Multimedia Card System Specification,

v4.2/4.3/4.4/4.41 including high-capacity (size > 2 GB) cards HC MMC.

Hardware reset as specified for eMMC cards is supported at ports #3

and #4 only.

• Fully compliant with SD command/response sets and Physical Layer

as defined in the SD Memory Card Specifications, v3.0 including

high-capacity SDHC cards up to 32 GB and SDXC cards up to 2TB.

• Fully compliant with SDIO command/response sets and

interrupt/read-wait mode as defined in the SDIO Card Specification,

Part E1, v1.10

• Fully compliant with SD Card Specification, Part A2, SD Host

Controller Standard Specification, v2.00

All four ports support:

• 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to

UHS-I SDR104 mode (104 MB/s max)

• 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52

MHz in both SDR and DDR modes (104 MB/s max)

However, the SoC-level integration and I/O muxing logic restrict the

functionality to the following:

• Instances #1 and #2 are primarily intended to serve as external slots or

interfaces to on-board SDIO devices. These ports are equipped with

“Card Detection” and “Write Protection” pads and do not support

hardware reset.

• Instances #3 and #4 are primarily intended to serve interfaces to

embedded MMC memory or interfaces to on-board SDIO devices.

These ports do not have “Card detection” and “Write Protection” pads

and do support hardware reset.

• All ports can work with 1.8 V and 3.3 V cards. There are two completely

independent I/O power domains for Ports #1 and #2 in four bit

configuration (SD interface). Port #3 is placed in his own independent

power domain and port #4 shares power domain with some other

interfaces.

VDOA VDOA Multimedia

Peripherals

The Video Data Order Adapter (VDOA) is used to re-order video data from

the “tiled” order used by the VPU to the conventional raster-scan order

needed by the IPU.

VPU Video Processing

Unit

Multimedia

Peripherals

A high-performing video processing unit (VPU), which covers many

SD-level and HD-level video decoders and SD-level encoders as a

multi-standard video codec engine as well as several important video

processing, such as rotation and mirroring.

See the i.MX 6Dual/6Quad reference manual (IMX6DQRM) for complete

list of VPU’s decoding/encoding capabilities.

WDOG-1 Watchdog Timer

Peripherals

The Watchdog Timer supports two comparison points during each

counting period. Each of the comparison points is configurable to evoke

an interrupt to the ARM core, and a second point evokes an external event

on the WDOG line.

Table 2. i.MX 6Dual/6Quad Modules List (continued)

Block

Mnemonic

Block Name Subsystem Brief Description

i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 4, 07/2015

18 Freescale Semiconductor Inc.

Modules List

3.1 Special Signal Considerations

The package contact assignments can be found in Section 6, “Package Information and Contact

Assignments.” Signal descriptions are defined in the i.MX 6Dual/6Quad reference manual

(IMX6DQRM). Special signal consideration information is contained in the Hardware Development

Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors

(IMX6DQ6SDLHDG).

3.2 Recommended Connections for Unused Analog Interfaces

The recommended connections for unused analog interfaces can be found in the section, “Unused analog

interfaces,” of the Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of

Applications Processors (IMX6DQ6SDLHDG).

WDOG-2

(TZ)

Watchdog

(TrustZone)

Timer

Peripherals

The TrustZone Watchdog (TZ WDOG) timer module protects against

TrustZone starvation by providing a method of escaping normal mode and

forcing a switch to the TZ mode. TZ starvation is a situation where the

normal OS prevents switching to the TZ mode. Such a situation is

undesirable as it can compromise the system’s security. Once the TZ

WDOG module is activated, it must be serviced by TZ software on a

periodic basis. If servicing does not take place, the timer times out. Upon

a time-out, the TZ WDOG asserts a TZ mapped interrupt that forces

switching to the TZ mode. If it is still not served, the TZ WDOG asserts a

security violation signal to the CSU. The TZ WDOG module cannot be

programmed or deactivated by a normal mode Software.

EIM NOR-Flash /PSRAM

interface

Connectivity

Peripherals

The EIM NOR-FLASH / PSRAM provides:

• Support 16-bit (in muxed IO mode only) PSRAM memories (sync and

async operating modes), at slow frequency

• Support 16-bit (in muxed IO mode only) NOR-Flash memories, at slow

frequency

• Multiple chip selects

XTALOSC Crystal Oscillator

interface

— The XTALOSC module enables connectivity to external crystal oscillator

device. In a typical application use-case, it is used for 24 MHz oscillator.

Table 2. i.MX 6Dual/6Quad Modules List (continued)

Block

Mnemonic

Block Name Subsystem Brief Description

i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 4, 07/2015

20 Freescale Semiconductor Inc.

Electrical Characteristics

4.1.2 Thermal Resistance

4.1.2.1 FCPBGA Package Thermal Resistance

Table 5 provides the FCPBGA package thermal resistance data.

MLB I/O supply voltage Supplies denoted as I/O supply -0.3 2.8 V

LVDS I/O supply voltage Supplies denoted as I/O supply -0.3 2.8 V

VDD_HIGH_IN supply voltage VDD_HIGH_IN -0.3 3.6 V

USB VBUS USB_H1_VBUS/USB_OTG_VBUS — 5.25 V

Input voltage on USB_OTG_DP, USB_OTG_DN,

USB_H1_DP, USB_H1_DN pins

USB_DP/USB_DN -0.3 3.63 V

Input/output voltage range V

out

-0.5 OVDD

+0.3 V

ESD damage immunity:

esd

• Human Body Model (HBM)

• Charge Device Model (CDM)

—

2000

500

Storage temperature range T

STORAGE

-40 150

OVDD is the I/O supply voltage.

Table 5. FCPBGA Package Thermal Resistance Data (Lidded)

Thermal Parameter Test Conditions Symbol Value Unit

Junction to Ambient

Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

Single-layer board (1s); natural convection

Per JEDEC JESD51-3 with the single layer board horizontal. Thermal test board meets JEDEC specification for the specified

package.

θJA

24 °C/W

Four-layer board (2s2p); natural convection

θJA

15 °C/W

Junction to Ambient

Single-layer board (1s); air flow 200 ft/min

Per JEDEC JESD51-6 with the board horizontal.

θJMA

17 °C/W

Four-layer board (2s2p); air flow 200 ft/min

θJMA

12 °C/W

Junction to Board

1,4

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

—R

θJB

5 °C/W

Junction to Case (top)

1,5

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1). The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the

interface layer.

—R

θJCtop

1 °C/W

Table 4. Absolute Maximum Ratings (continued)

Parameter Description Symbol Min Max Unit

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