MT2523芯片详细规格：集成MCU与低功耗GNSS的多合一解决方案

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MT2523是一款由联发科（Mediatek）推出的高度集成芯片，它属于MT2523系列的一部分，包括MT2523D和MT2523G型号。这款芯片集成了多种功能，使其在可穿戴设备领域具有广泛的应用潜力。MT2523G的核心组件是基于ARM Cortex-M4架构的微控制器单元（MCU），配备了浮点运算单元（FPU），内存配置为4MB的片上静态随机存取存储器（PSRAM）和4MB闪存，这提供了强大的处理能力和存储空间。该芯片还支持多种接口，如通用串行总线（UART）、I2C、串行外围设备接口（SPI）、立体声数字音频接口（I2S）、脉宽调制（PWM）、安全数字输入输出（SDIO）、多媒体卡接口（MSDC）、通用串行总线（USB）、PC卡接口（PCMIF）、模拟到数字转换器（ADC）以及双数字麦克风，这些特性使得MT2523G非常适合于需要低功耗、多连接和音频采集的设备，例如智能手表、健身追踪器或便携式健康监测设备。 MT2523Series Datasheet的版本为1.4，发布日期为2017年1月13日。该文档包含了联发科的专有信息，用户必须已签署并遵守适用的许可协议（License Agreement），即只有获得明确授权的用户（Permitted User）才能使用或复制这份文档。未经授权的使用或泄露文档将受到严格禁止。文档提供“原样”基础，联发科对文档内容不作任何保证，也不承担因使用或无法使用此文档而产生的任何索赔责任。芯片规格可能未经通知就进行更改。 MT2523G是一款针对低功耗和多功能应用设计的嵌入式系统解决方案，其高性能的微控制器、丰富的接口选项以及兼容许可协议的规定，使其成为现代可穿戴设备中不可或缺的组件，尤其适用于那些对功耗管理、数据传输和音频功能有较高要求的设备。开发者在设计产品时需确保遵循文档中的规定，以充分利用MT2523G的全部潜能。

MT2523 Series Datasheet

Page 12 of 124

This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

• 128-entry command queue for command transmission.

• Supports three types of video modes — sync-event, sync-pulse and burst mode.

• Supports non-continuous high-speed transmission in data lanes.

• Supports command mode frame transmission-free run.

• Supports peripheral tearing effect (TE) and external TE signal detection.

• Low power mode control.

• Low frame-rate (LFR) technique.

1.2.3. 2D accelerator

• Supports 32-bpp ARGB8888, 24-bpp RGB888, 16-bpp RGB565 and 24-bpp ARGB6666.

• Four layers of overlay with individual color format, window size, source key, constant alpha and rotation.

• Rectangle fill with constant.

• Bit-boundary block transfer (BitBlt). Supports up to seven rotation types.

• Alpha blending with seven rotation types, per-pixel alpha and pre-multiplied alpha.

• Font drawing. Normal font and anti-aliasing font (Display Adaptive Ambient Light Controller).

1.2.4. Display adaptive ambient light controller

• 33-bin weighted histogram.

• DRE enhancement for sunlight visibility.

• CABC compensation for backlight power saving.

1.3. Audio

Using a highly integrated mixed-signal audio front-end, the MT2523 series architecture enables audio interfacing

with direct connection to the audio transducers. The audio interface integrates A/D converters for voice band, as

well as high-resolution stereo D/A converters for both audio and voice bands.

1.3.1. Audio CODEC

• Supports AAC and SBC codecs for Bluetooth audio.

• Supports CVSD and mSBC codecs for Bluetooth speech.

• Pure PCM playback for 8-48kHz sample rate.

• Pure PCM record for 8kHz and 16kHz sample rates.

1.3.2. Audio interface and audio front-end

• Pure PCM record for 8kHz and 16kHz sample rates.

• Supports master I2S interface.

• Supports master PCM interface.

• Supports dual PDM microphone.

MT2523 Series Datasheet

Page 13 of 124

This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

• High-resolution D/A converters for stereo audio playback.

• Voice band A/D converter support.

• Stereo to mono conversion.

1.4. Bluetooth

MT2523 series offers a highly integrated Bluetooth radio and baseband processor. Only a minimum of external

components is required.

MT2523 series is fully compliant with Bluetooth version 4.2, upgradable to later versions, including BR/EDR and

Bluetooth LE and offers enhanced data rates of up to 3Mbps. It also provides the coexistence protocol with IEEE

802.11 protocol.

1.4.1. Radio

• Fully compliant with Bluetooth core specification 4.2.

• Low-IF architecture with high degree of linearity and high order channel filter.

• Integrated T/R switch and balun.

• Fully integrated PA provides 7.5dBm output power.

• -95dBm sensitivity with interference rejection performance.

• Hardware AGC dynamically adjusts receiver performance in changing environments.

1.4.2. Baseband

• Up to seven simultaneous active ACL links.

• Up to eight simultaneous active Bluetooth LE links.

• A single SCO or eSCO link with CVSD/mSBC coding.

• Up to two simultaneous ACL slave links and four simultaneous Bluetooth LE links for audio or voice

application, basic rate A2DP.

• AFH and PTA collaborative support for WLAN/Bluetooth coexistence.

• Idle mode and sleep mode enables ultra-low power consumption.

• Supports PCM interface and built-in programmable transcoders for linear voice with re-transmission.

• Built-in hardware modem engine for access code correlation, header error correction, forward error

correction, CRC, whitening and encryption.

• Channel quality driven data rate adaptation.

• Channel assessment for AFH.

1.4.3. Core

• Feasibility Bluetooth host subsystem in Cortex-M4 MCU to support customized applications.

• Embedded processor for Bluetooth controller subsystem with built-in memory system.

• Fully verified ROM based system with code patch for feature enhancement.

MT2523 Series Datasheet

Page 15 of 124

This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

2. Functional Overview

2.1. Host Processor Subsystem

2.1.1. ARM® Cortex®-M4 with FPU

The Cortex-M4 with FPU is a low-power processor with 3-stage pipeline Harvard architecture. It has reduced pin

count and low power consumption and delivers very high performance efficiency and low interrupt latency,

making it ideal for embedded microcontroller products.

The processor incorporates:

• IEEE754-compliant single-precision floating-point computation unit (FPU).

• A Nested Vectored Interrupt Controller (NVIC) to achieve low latency interrupt processing.

• Enhanced system debugging with extensive breakpoint and trace capabilities.

• An optional Memory Protection Unit (MPU) to ensure platform security robustness.

The Cortex-M4 executes the Thumb®-2 instruction set with 32-bit architecture, with the high code density of 8-bit

and 16-bit microcontrollers. The instruction set is fully backward compatible with Cortex-M3/M0+.

MT2523 series has further enhanced the Cortex-M4 with floating point processor to reduce the power by another

11% (in Dhrystone) compared to the original Cortex-M4. Low power consumption is a significant feature for IoT

and Wearables application development.

2.1.2. Cache controller

A configurable 32kB cache is implemented to improve the code fetch performance when the CPU accesses a non-

zero wait-state memory such as EMI, external flash or boot ROM through the on-chip bus.

The core cache is a small block of memory containing a copy of small portion of cacheable data in the external

memory. If the CPU reads a cacheable datum, the datum will be copied to the core cache. Once the CPU requests

the same datum again, it can be obtained directly from the core cache (called cache hit) instead of fetching it again

from the external memory to achieve zero wait-state latency.

The cache can be disabled and this block of memory can be turned into tightly coupled memory (TCM), a high-

speed memory for normal data storage. The sizes of TCM and cache can be set to one of the following four

configurations:

• 32kB cache, 128kB TCM

• 16kB cache, 144kB TCM

• 8kB cache, 152kB TCM

• 0kB cache, 160kB TCM

2.1.3. Memory management

Three types of memories are implemented for use:

1) On-die memories (SRAMs) up to 160kB at CPU clock speed with zero wait state.

MT2523 Series Datasheet

Page 16 of 124

This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

2) Embedded flash to store programs and data.

3) Embedded pseudo SRAM (PSRAM) for application storage.

160kB SRAMs are composed of TCMs and L1 caches. L1 cache (up to 32kB) is implemented to improve processor

access performance of the long latency memories (flash and PSRAM).

TCMs are designed for high-speed, low latency and low power demanding applications. Each TCM has its own

power state; active, retention or power-down. TCM must be in active state for normal read and write access.

Retention state saves the SRAM content and consumes the minimum leakage current with no access. Power-down

loses the content and consumes almost zero power.

Other internal AHB masters including DMA or multimedia sub-system for low power applications can also access

the TCMs. These applications can run on TCM without powering on PSRAM or Flash to save more power.

Boot ROM is also implemented for processor boot–up and its content is unchangeable.

2.1.4. Memory Protection Unit

The Memory Protection Unit (MPU) is an optional component to manage the CPU access to memory. The MPU

provides full support for:

• Protection regions (up to 8 regions and can be further divided up into 8 sub-regions).

• Overlapping protection regions, with region priority.

• Access permissions.

• Exporting memory attributes to the system.

The MPU is useful for applications where a critical code has to be protected against the misbehavior of other tasks.

It can be used to define access rules, enforce privilege rules and separate processes.

2.1.5. Nested Vectored Interrupt Controller

The Nested Vectored Interrupt Controller (NVIC) supports up to 64 maskable interrupts and 16 interrupt lines of

Cortex-M4 MCU with 64 priority levels. The NVIC and the processor core interface are closely coupled to enable

low latency interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge

of the stacked or nested interrupts to enable tail-chaining of interrupts. The processor supports both level and

pulse interrupts with programmable active-high or low control.

2.1.6. External Interrupt Controller

The external interrupt or event controller (EINT) consists of 32 edge/level detector lines used to generate interrupt

or event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge,

both and level) and can be masked independently. A pending register maintains the status of the interrupt

requests. Up to 31 GPIOs can be connected to 20 external interrupt lines.

2.1.7. Bus architecture

To better support various IoT applications, MT2523 series adopts 32-bit multi-AHB matrix to provide low-power,

fast and flexible data operation. Table 2.1-1 shows the interconnections between bus masters and slaves.

• The bus masters include the Cortex-M4 MCU, four SPI masters, SPI slave, Debug system, Multimedia (MM)

system, USB and three DMAs.

• The bus slaves include the Always On (AO) domain APB peripherals, Power Down (PD) domain APB

peripherals, TCM, SFC, EMI, MDSYS and BTSYS.

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