Intel X86处理器L3缓存攻击：FLUSH+RELOAD - 高精度低噪音信息泄露

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"Flush+Reload 是一项针对英特尔 X86 处理器架构的高级分辨率、低噪音的 L3 缓存侧通道攻击技术，首次由 Yuval Yarom 和 Katrina Falkner 在 2014 年的论文中提出。该研究专注于多租户系统中常见的内存共享策略，即非信任进程共享内存页以减少内存占用。然而，这项工作揭示了一个潜在的安全漏洞：Intel X86 处理器在处理共享页面时存在信息泄露的风险。 Flush+Reload 攻击利用了这一弱点，通过监视缓存状态来窥探共享页面中的内存访问模式。与以往的缓存侧信道攻击不同，它特别针对最后级缓存（L3），这意味着攻击者和受害者并不需要共享执行核心，这显著增加了攻击的隐蔽性。这种技术的关键在于，攻击者能够通过向目标缓存线发起'flush'操作，然后通过测量后续'reload'操作时缓存填充的时间来推断出数据访问情况，即使在不同的操作系统环境或虚拟机中也能进行跨进程监控。研究人员展示了 Flush+Reload 攻击的实际效能，通过在运行 GnuPG 1.4.13 的程序中提取私有加密密钥。实验结果显示，平均而言，该攻击能够恢复到96.7%的密钥位，表明其具有很高的信息获取能力。由于 L3 缓存通常具有较大的容量和较高的访问速度，攻击者可以利用这一特性进行高效且精确的攻击，这对信息安全构成了严重威胁，特别是对于依赖于内存隔离的敏感应用和多用户环境。为了保护系统免受此类攻击，开发者和安全专家需要对缓存管理机制有深入理解，并采取相应的防护措施，如缓存一致性协议增强、随机化内存访问以及在设计阶段考虑缓解缓存侧信道攻击的策略。同时，硬件厂商也需要进一步改进处理器设计，以降低此类攻击的可能性。 Flush+Reload 的发现不仅提升了我们对现代处理器安全的认识，也推动了密码学和系统安全领域的研究，促使业界持续寻求更加安全的内存管理实践和防御手段。"

share a 6MB L3 cache, also known as the Last-Level

Cache, or LLC.

The unit of memory in a cache is a line which contains

a ﬁxed number of bytes. A cache consists of multiple

cache sets each of which stores a ﬁxed number of cache

lines. The number of cache lines in a set is the cache

associativity. Each memory line can be cached in any of

the cache lines of a single cache set. The size of cache

lines in the Core i5-3470 processor is 64 bytes. The L1

and L2 caches are 8-way associative and the L3 cache is

12-way associative.

An important feature of the LLC in modern Intel pro-

cessors is that it is an inclusive cache. That is, the LLC

contains copies of all of the data stored in the lower cache

levels. Consequently, ﬂushing or evicting data from the

LLC also remove said data from all other cache levels of

the processor. Our attack exploits this cache behaviour.

Retrieving data from memory or from cache levels

closer to memory takes longer than retrieving it from

cache levels closer to the core. This difference in tim-

ing has been exploited for side-channel attacks. Side-

channel attacks target information that an implementa-

tion of an algorithm leaks through its interaction with

its environment. To exploit the timing difference, an at-

tacker sets the cache to a known state prior to a victim

operation. It can, then, use one of two methods to de-

duce information on the victim’s operation [43]. The

ﬁrst method is measuring the time it takes for the vic-

tim to execute the operation. As this time depends on

the state of the cache when the victim starts the opera-

tion, the attacker can deduce the cache sets accessed by

the victim and, therefore, learn information on the vic-

tim [5, 9, 57]. The second approach is for the attacker to

measure the time it takes for the attacker to access data

after the victim’s operation. This time is dependent on

the cache state prior to the victim operation as well as

on the changes the victim operation caused in the cache

state [1, 2,4, 14, 19, 47, 61].

Most prior work on cache side-channel attacks relies

on the victim and spy executing within the same process-

ing core. One reason for that is that many of the attacks

suggested require the victim to be stopped while the spy

performs the attack. To that aim, the attack is combined

with an attack on the scheduler that allows the spy pro-

cess to interrupt and block the victim.

Another reason for attacking within the same core is

that the attacks focus on the L1 cache level, which is not

shared between cores. The large size of the LLC hin-

ders attacks both because setting it to a known state takes

longer than with smaller caches and because the virtual

memory used by the operating system masks the map-

ping of memory addresses to cache sets. Furthermore,

as most of the memory activity occurs at the L1 cache

level, less information can be extracted from LLC activ-

ity. Some prior works do use the LLC as an information

leak channel [46,47,60]. However, due to the cache size,

these channels have a low bandwidth.

We now proceed to describe the RSA encryption.

2.3 RSA

RSA [48] is a public-key cryptographic system that sup-

ports encryption and signing. Generating an encryption

system requires the following steps:

• Randomly selecting two prime numbers p and q and

calculating n = pq.

• Choosing a public exponent e. GnuPG uses e =

65537.

• Calculating a private exponent d ≡ e

−1

(mod (p−

1)(q −1)).

The generated encryption system consists of:

• The public key is the pair (n,e).

• The private key is the triple (p,q,d).

• The encrypting function is E(m) = m

mod n.

• The decrypting function is D(c) = c

mod n.

CRT-RSA is a common optimisation for the imple-

mentation of the decryption function. It splits the se-

cret key d into two parts d

= d mod (p − 1) and d

d mod (q −1), computes two parts of the message: m

mod p and m

= c

mod q. m is then computed

from m

and m

using Garner’s formula [25]:

h = (m

− m

)(q

−1

mod p) mod p

m = m

+ hq

To compute the encryption and decryption func-

tions, GnuPG versions before 4.1.14 and the related

libgcrypt before version 1.5.3 use the square-and-

multiply exponentiation algorithm [28]. Square-and-

multiply computes x = b

mod m by scanning the bits

of the binary representation of the exponent e. Given a

binary representation of e as 2

n−1

+· · · 2

, square-

and-multiply calculates a sequence of intermediate val-

ues x

n−1

,...,x

such that x

= b

be/2

mod m using the

formula x

i−1

= x

i−1

. Figure 2 shows a pseudo-code

implementation of square-and-multiply.

As can be seen from the implementation, computing

the exponent consists of sequence of Square and Mul-

tiply operations, each followed by a Modulo Reduce.

This sequence corresponds directly with the bits of the

exponent. Each occurrence of Square-Reduce-Multiply-

Reduce within the sequence corresponds to a bit whose

value is 1. Occurrences of Square-Reduce that are not

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