镁光DDR3L 1.35V 1Gb内存手册：低电压兼容与特性概览

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本文档是镁光公司关于DDR3L SDRAM的详细手册，针对的是MT41K系列内存芯片，如MT41K256M4、MT41K128M8和MT41K64M16，这些产品支持低电压工作模式，特别适合对功耗和电压敏感的应用。DDR3L的显著特点是其工作电压降低至1.35V（允许的范围为1.283V至1.45V），这使得它在保持性能的同时，能够节省能源，符合现代电子设备对低功耗设计的需求。该内存的其他关键特性包括： 1. 向后兼容：尽管设计为1.35V运行，但这些DDR3L芯片仍然可以与1.5V DDR3 SDRAM设备兼容，只需在1.5V ± 0.075V的电压范围内工作。 2. 差分双向数据 strobe 功能，提高了信号传输的稳定性。 3. 采用8n位预取架构，提升数据读取速度和效率。 4. 内部有8个独立的银行，支持多通道数据传输，提高带宽能力。 5. 动态和静态确定的 ODT（Output Driver Strength）控制数据、strobe 和 mask 信号，提供灵活性。 6. 可编程的 CAS（Column Address Strobe）延迟，包括读取（CL）、写入附加（AL）和写入（CWL）延迟，以适应不同的系统需求。 7. 固定的突发长度（BL）为8字节，以及突发切片（BC）为4字节，可以通过模制寄存器集（MRS）进行选择或动态切换。 8. 支持在运行时选择BC4或BL8模式，提供了更高级别的灵活性。 9. 自动自刷新（ASR）功能，可在无需外部干预的情况下自动进入低功耗状态，延长电池寿命。 10. 写平滑技术（Write Leveling）确保了数据一致性，减少写操作对存储单元的影响。 11. 多用途寄存器支持高级配置选项。 12. 输出驱动器校准功能，确保最佳信号质量。此外，手册还列出了温度管理特性，包括工作温度限制（95°C，最大刷新周期为-64ms，在85°C以上时可延长至8192个周期），以及自刷新模式下的不同温度下的自刷新周期，确保在高温环境中的可靠运行。总结来说，镁光DDR3L手册提供了全面的技术细节，帮助工程师理解和使用这些低电压、高性能的内存模块，以满足不同应用场景的特定要求。

Figure 4: 128 Meg x 8 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

Command

decode

A[13:0]

BA[2:0]

Address

8,192

I/O gating

DM mask logic

Column

decoder

Bank 0

memory

array

(16,384 x 128 x 64)

Bank 0

row-

address

latch

and

decoder

16,384

Sense amplifiers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

DQS, DQS#

Columns 0, 1, and 2

ZQCL, ZQCS

To ODT/output drivers

READ

drivers

DQ[7:0]

READ

FIFO

and

data

MUX

Data

Bank 1

Bank 2

Bank 3

DM/TDQS

(shared pin)

TDQS#

CK, CK#

DQS, DQS#

ZQ CAL

RZQ

CK, CK#

RAS#

WE#

CAS#

CS#

ODT

CKE

RESET#

CK, CK#

DLL

DQ[7:0]

DQ8

(1 . . . 8)

(1, 2)

sw1

sw2

DDQ

TT,nom

TT(WR)

sw1

sw2

DDQ

TT,nom

TT(WR)

sw1

sw2

DDQ

TT,nom

TT(WR)

BC4 (burst chop)

BC4

WRITE

drivers

and

input

logic

Data

interface

Column 2

(select upper or

lower nibble for BC4)

(128

x64)

ODT

control

SSQ

A12

OTF

Figure 5: 64 Meg x 16 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

Command

decode

A[12:0]

BA[2:0]

Address

(128

x128)

16,384

I/O gating

DM mask logic

Column

decoder

Bank 0

memory

array

(8192 x 128 x 128)

Bank 0

row-

address

latch

and

decoder

8,192

Sense amplifiers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

128

LDQS, LDQS#, UDQS, UDQS#

Column 0, 1, and 2

Columns 0, 1, and 2

ZQCL, ZQCS

To ODT/output drivers

BC4

READ

drivers

DQ[15:0]

READ

FIFO

and

data

MUX

Data

BC4 (burst chop)

Bank 1

Bank 2

Bank 3

LDM/UDM

CK, CK#

LDQS, LDQS#

UDQS, UDQS#

ZQ CAL

RZQ

ODT

CKE

CK, CK#

RAS#

WE#

CAS#

CS#

RESET#

CK, CK#

DLL

DQ[15:0]

(1 . . . 16)

(1 . . . 4)

(1, 2)

sw1

sw2

DDQ

TT,nom

TT(WR)

BC4

sw1

sw2

DDQ

TT,nom

TT(WR)

sw1

sw2

DDQ

TT,nom

TT(WR)

Column 2

(select upper or

lower nibble for BC4)

Data

interface

WRITE

drivers

and

input

logic

ODT

control

SSQ

A12

OTF

1Gb: x4, x8, x16 DDR3L SDRAM

Functional Block Diagrams

PDF: CCMTD-1725822587-774

1Gb_DDR3L.pdf - Rev. L EN 9/18

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions

Symbol Type Description

A[9:0], A10/AP,

A11, A12/BC#,

A13

Input Address inputs: Provide the row address for ACTIVATE commands, and the column ad-

dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out

of the memory array in the respective bank. A10 sampled during a PRECHARGE com-

mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected

by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a

LOAD MODE command. Address inputs are referenced to V

REFCA

. A12/BC#: when enabled

in the mode register (MR), A12 is sampled during READ and WRITE commands to deter-

mine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop,

LOW = BC4 burst chop).

BA[2:0] Input Bank address inputs: BA[2:0] define to which bank an ACTIVATE, READ, WRITE, or PRE-

CHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1,

MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to

REFCA

CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and the negative edge of CK#. Out-

put data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal cir-

cuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is depend-

ent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW pro-

vides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle) or active

power-down (row active in any bank). CKE is synchronous for power-down entry and exit

and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (exclud-

ing CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (ex-

cluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to V

REFCA

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command

decoder. All commands are masked when CS# is registered HIGH. CS# provides for exter-

nal rank selection on systems with multiple ranks. CS# is considered part of the command

code. CS# is referenced to V

REFCA

DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when

DM is sampled HIGH along with the input data during a write access. Although the DM

ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM

is referenced to V

REFDQ

. DM has an optional use as TDQS on the x8 device.

ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) ter-

mination resistance internal to the DDR3 SDRAM. When enabled in normal operation,

ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the

x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the

LOAD MODE command. ODT is referenced to V

REFCA

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being

entered and are referenced to V

REFCA

RESET# Input Reset: RESET# is an active LOW CMOS input referenced to V

. The RESET# input receiver

is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V

and DC LOW ≤

0.2 × V

DDQ

. RESET# assertion and de-assertion are asynchronous.

DQ[3:0] I/O Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are refer-

enced to V

REFDQ

1Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

PDF: CCMTD-1725822587-774

1Gb_DDR3L.pdf - Rev. L EN 9/18

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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