PRELIMINARY
16 • AR9344 Highly-Integrated 802.11n 2x2 2.4/5 GHz Premium SoC Atheros Communications, Inc.
16 • December 2010 COMPANY CONFIDENTIAL
8.19.19 Checksum Burst Control
(ARB_BURST) ...........................298
8.19.20 DMA Reset (RESET_DMA) ... 298
8.19.21 Checksum Configuration
(CONFIG) ..................................298
8.20 UART1 (High-Speed) Registers ........ 299
8.20.1 UART1 Transmit and Rx FIFO
Interface (UART1_DATA) .......299
8.20.2 UART1 Configuration and Status
(UART1_CS) ..............................300
8.20.3 UART1 Clock (UART1_CLOCK) .
301
8.20.4 UART1 Interrupt/Control Status
(UART1_INT) ............................301
8.20.5 UART1 Interrupt Enable
(UART1_INT_EN) ....................302
8.21 GMAC0/GMAC1 Registers ..............303
8.21.1 MAC Configuration 1 ..............308
8.21.2 MAC Configuration 2 ..............309
8.21.3 IPG/IFG .....................................309
8.21.4 Half-Duplex ...............................310
8.21.5 Maximum Frame Length ......... 310
8.21.6 MII Configuration .....................311
8.21.7 MII Command ...........................311
8.21.8 MII Address ...............................312
8.21.9 MII Control ................................312
8.21.10 MII Status .................................312
8.21.11 MII Indicators ..........................312
8.21.12 Interface Control .....................313
8.21.13 Interface Status ........................314
8.21.14 STA Address 1 .........................315
8.21.15 STA Address 2 .........................315
8.21.16 ETH_FIFO RAM Configuration 0
316
8.21.17 ETH Configuration 1 .............. 317
8.21.18 ETH Configuration 2 .............. 317
8.21.19 ETH Configuration 3 .............. 317
8.21.20 ETH Configuration 4 .............. 318
8.21.21 ETH Configuration 5 .............. 318
8.21.22 Tx/Rx 64 Byte Frame Counter
(TR64) .........................................319
8.21.23 Tx/Rx 65-127 Byte Frame Counter
(TR127) .......................................319
8.21.24 Tx/Rx 128-255 Byte Frame
Counter (TR255) ........................319
8.21.25 Tx/Rx 256-511 Byte Frame
Counter (TR511) ........................ 319
8.21.26 Tx/Rx 512-1023 Byte Frame
Counter (TR1K) ......................... 320
8.21.27 Tx/Rx 1024-1518 Byte Frame
Counter (TRMAX) .................... 320
8.21.28 Tx/Rx 1519-1522 Byte VLAN
Frame Counter (TRMGV) ........ 320
8.21.29 Receive Byte Counter (RXBT) 320
8.21.30 Receive Packet Counter (RPKT) .
321
8.21.31 Receive FCS Error Counter (RFCS)
321
8.21.32 Receive Multicast Packet Counter
(RMCA) ...................................... 321
8.21.33 Receive Broadcast Packet Counter
(RBCA) ....................................... 321
8.21.34 Receive Control Frame Packet
Counter (RXCF) ........................ 322
8.21.35 Receive Pause Frame Packet
Counter (RXPF) ......................... 322
8.21.36 Receive Unknown OPCode Packet
Counter (RXUO) ....................... 322
8.21.37 Receive Alignment Error Counter
(RALN) ....................................... 322
8.21.38 Receive Frame Length Error
Counter (RFLR) ......................... 323
8.21.39 Receive Code Error Counter
(RCDE) ....................................... 323
8.21.40 Receive Carrier Sense Error
Counter (RCSE) ......................... 323
8.21.41 Receive Undersize Packet Counter
(RUND) ...................................... 323
8.21.42 Receive Oversize Packet Counter
(ROVR) ....................................... 324
8.21.43 Receive Fragments Counter
(RFRG) ........................................ 324
8.21.44 Receive Jabber Counter (RJBR) 324
8.21.45 Receive Dropped Packet Counter
(RDRP) ....................................... 324
8.21.46 Transmit Byte Counter (TXBT) 325
8.21.47 Transmit Packet Counter (TPKT)
325
8.21.48 Transmit Multicast Packet Counter
(TMCA) ...................................... 325
8.21.49 Transmit Broadcast Packet
Counter (TBCA) ........................ 325
8.21.50 Transmit Pause Control Frame
Counter (TXPF) ......................... 326