ADV7180: 10-Bit SDTV Video Decoder with Auto NTSC/PAL/SECAM Support

需积分: 9 25 浏览量更新于2024-07-23 收藏 2.01MB PDF 举报

"ADV7180是一款10位4倍过采样SDTV（标准清晰度电视）视频解码器的数据手册，适用于汽车应用。这款芯片支持全球范围内的NTSC、PAL和SECAM彩色解调。" 本文档详细介绍了ADV7180的主要特点和功能，它是Analog Devices公司推出的一款高性能视频解码器，旨在处理各种视频输入信号，如复合视频（CVBS）、S-Video（Y/C）和分量视频（YPrPb）。以下是其关键特性和技术规格的详细解析： 1. **10-Bit, 4×Oversampling**： ADV7180采用10位分辨率，提供4倍过采样技术，这在处理CVBS输入时使用。过采样有助于提高信噪比，减少量化噪声，从而获得更清晰的视频图像。 2. **SDTV Video Decoder**：这款解码器专为标准清晰度电视信号设计，能够解码并处理不同制式的视频信号，包括北美常用的NTSC，欧洲和大部分地区的PAL，以及法国和其他地方的SECAM制式。 3. **3 Video Input Channels**： ADV7180配备了三个视频输入通道，每个通道都集成了抗混叠滤波器，可以处理复合视频、S-Video和分量视频输入。这种多通道设计使得设备能够灵活地连接到不同的视频源。 4. **On-Chip Antialiasing Filter**：内置的抗混叠滤波器有助于消除高频信号成分，防止在数字化过程中出现混叠现象，确保视频信号的质量。 5. **5-Line Adaptive Comb Filters and CTI/DNR**：五线自适应梳状滤波器用于分离色度和亮度信号，增强图像的清晰度。同时，芯片还支持色带抑制（CTI）和降噪（DNR）功能，进一步提升视频质量，减少干扰和噪声。 6. **Automotive Qualification**： ADV7180符合汽车行业的质量标准，意味着它可以在苛刻的汽车环境中稳定工作，满足汽车电子系统对可靠性和耐用性的严格要求。 7. **Technical Support**： Analog Devices提供了广泛的技术支持，用户可以通过其官方网站www.analog.com获取最新的技术资料和帮助。 ADV7180是一款针对多种视频格式和环境设计的高效解码器，适合应用于需要高质量视频处理的汽车电子系统和其他领域。其先进的过采样技术和视频增强功能确保了即使在复杂的视频信号条件下也能提供出色的图像质量。

ADV7180 Data Sheet

Rev. I | Page 16 of 116

Pin No. Mnemonic Type Description

40 AVDD P Analog Supply Voltage (1.8 V).

RESET

System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset

the ADV7180 circuitry.

52 ALSB I

This pin selects the I

C address for the ADV7180. For ALSB set to Logic 0, the address selected

for a write is Address 0x40; for ALSB set to Logic 1, the address selected is Address 0x42.

53 SDATA I/O I

C Port Serial Data Input/Output Pin.

54 SCLK I I

C Port Serial Clock Input. The maximum clock rate is 400 kHz.

63 FIELD O Field Synchronization Output Signal.

64 VS O Vertical Synchronization Output Signal.

Data Sheet ADV7180

Rev. I | Page 17 of 116

48-LEAD LQFP

INTRQ

VS/FIELD

DVDD

DGND

GPO2

GPO3

SCLK

SDATA

ALSB

RESET

VFEFN

AVDD

AGND

VREFP

AGND

PVDD

DVDDIO

SFL

DVDDIO

GPO0

GPO1

DGND

NC = NO CONNECT

DGND

LLC

XTAL1

XTAL

DVDD

DGND

PWRDWN

AGND

ELPF

PIN 1

ADV7180

LQFP

TOP VIEW

(Not to Scale)

05700-062

Figure 11. 48-Lead LQFP Pin Configuration

Table 12. 48-Lead LQFP Pin Function Descriptions

Pin No. Mnemonic Type Description

1, 13, 19, 43 DGND G Digital Ground.

2, 4 DVDDIO P Digital I/O Supply Voltage (1.8 V to 3.3 V).

3 SFL O

Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the

subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder.

5, 6, 41, 42 GPO0 to GPO3 O General-Purpose Outputs. These pins can be configured via I

C to allow control of external devices.

7 to 12, 20, 22 P7 to P2, P1, P0 O Video Pixel Output Port. See Table 100 for output configuration for 8-bit and 16-bit modes.

14 LLC O

This is a line-locked output clock for the pixel data output by the ADV7180. It is nominally

27 MHz but varies up or down according to video line length.

15, 48 NC No Connect Pins. These pins are not connected internally.

16 XTAL1 O

This pin should be connected to the 28.6363 MHz crystal or left as a no connect if an external 1.8 V,

28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode, the crystal

must be a fundamental crystal.

17 XTAL I

This is the input pin for the 28.6363 MHz crystal, or this pin can be overdriven by an external 1.8 V,

28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.

18, 44 DVDD P Digital Supply Voltage (1.8 V).

PWRDWN

I A logic low on this pin places the ADV7180 in power-down mode.

23, 28, 32 AGND G Analog Ground.

24 ELPF I The recommended external loop filter must be connected to the ELPF pin, as shown in Figure 59.

25 PVDD P PLL Supply Voltage (1.8 V).

26, 27, 33 to 36 A

1 to A

6 I Analog Video Input Channels.

29 VREFP O Internal Voltage Reference Output. See Figure 59 for recommended output circuitry.

30 VREFN O Internal Voltage Reference Output. See Figure 59 for recommended output circuitry.

31 AVDD P Analog Supply Voltage (1.8 V).

RESET

System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset

the ADV7180 circuitry.

38 ALSB I

This pin selects the I

C address for the ADV7180. For ALSB set to Logic 0, the address selected

for a write is Address 0x40; for ALSB set to Logic 1, the address selected is Address 0x42.

39 SDATA I/O I

C Port Serial Data Input/Output Pin.

40 SCLK I I

C Port Serial Clock Input. The maximum clock rate is 400 kHz.

45 VS/FIELD O Vertical Synchronization Output Signal/Field Synchronization Output Signal.

INTRQ

Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video

(see Table 108).

47 HS O Horizontal Synchronization Output Signal.

ADV7180 Data Sheet

Rev. I | Page 18 of 116

POWER SUPPLY SEQUENCING

POWER-UP SEQUENCE

The power-up sequence for the ADV7180 is to power up all power

supplies simultaneously. If this is not possible, the 3.3 V supply

VDDIO

) must be established first. When the 3.3 V supply is stable,

power up the 1.8 V supplies (D

VDD

, P

VDD

, and A

VDD

) as quickly as

possible. Until the 1.8 V supplies are fully established, all digital

pins are in an undefined state.

During power-up, all supplies must adhere to the specifications

listed in the Absolute Maximum Ratings section.

Take care to ensure that a lower rated supply does not go above

a higher rated supply. For example, the 3.3 V D

VDDIO

supply must

never drop below a 1.8 V supply such as the D

VDD

, P

VDD

, or A

VDD

To power up the ADV7180, follow these steps.

1. Assert the

PWRDWN

pin and the

RESET

pin (that is, pull

the pins low.)

2. Power up the 3.3 V supply (D

VDDIO

) and 1.8 V supplies

VDD

, P

VDD

, and A

VDD

) simultaneously.

1, 2

3. When all supplies are fully asserted, pull the

PWRDWN

pin high. Note that this step can be ignored on the 32-lead

LFCSP, as the

PWRDWN

pin is not available.

4. Wait 5 ms, then pull the

RESET

pin high.

5. When all power supplies, the

PWRDWN

pin, and the

RESET

pin are powered up and stable, wait an additional 5 ms

before initiating I

C communication with the ADV7180.

POWER-DOWN SEQUENCE

The ADV7180 supplies can be deasserted simultaneously as

long as D

VDDIO

does not go below a lower rated supply.

UNIVERSAL POWER SUPPLY

The ADV7180 can operate with a D

VDDIO

supply at a nominal

value of 1.8 V. Therefore, it is possible to power up all the supplies

for the ADV7180 (D

VDD

, A

VDD

, P

VDD

, and D

VDDIO

) to 1.8 V.

When D

VDDIO

is at a nominal value of 1.8 V, power up the

ADV7180 in the following manner:

1. Follow the power-up sequence described in the Power-Up

Sequence section, but power up the D

VDDIO

supply to 1.8 V

instead of 3.3 V. In addition, power up the

PWRDWN

and the

RESET

pin to 1.8 V instead of 3.3 V.

2. Set the drive strengths of the digital outputs of the ADV7180

to their maximum setting. See the Global Pin Control section.

3. Connect any pull-up resistors connected to pins on the

ADV7180, such as the SCLK pin and the SDATA pin, to

1.8 V, rather than 3.3 V.

If it is not possible to power up the D

VDDIO

and 1.8 V supplies simultaneously,

the D

VDDIO

supply must be powered up first. When the D

VDDIO

is stable, power

up the 1.8 V supplies as quickly as possible.

During power-up, take care to ensure that the D

VDDIO

supply never drops

below any of the 1.8 V supplies.

05700-100

3.3V

1.8V

VOLTAGE

TIME

SUPPLIES

POWER-UP

3.3V SUPPLIES

PWRDWN PIN

POWER-UP

RESET PIN

POWER-UP

5ms

RESET

OPERATION

RESET PIN

1.8V

SUPPLIES

5ms

WAIT

Figure 12. Power-Up Sequence of the 40-Lead LFCSP, 48-Lead LQFP, and 64-Lead LQFP

05700-101

3.3V

1.8V

VOLTAGE

TIME

SUPPLIES

POWER-UP

3.3V SUPPLIES

RESET PIN

POWER-UP

5ms

RESET

OPERATION

RESET PIN

1.8V

SUPPLIES

5ms

WAIT

Figure 13. Power-Up Sequence of the 32-Lead LFCSP

ADV7180 Data Sheet

Rev. I | Page 20 of 116

INPUT CONFIGURATION

The following are the two key steps for configuring the

ADV7180 to correctly decode the input video:

1. Use INSEL[3:0] to configure the routing and format decoding

(CVBS, Y/C, or YPrPb). For the 64-lead and 48-lead LQFP,

see Table 13. For the 40-lead and 32-lead LFCSP, see Table 14.

2. If the input requirements are not met using the INSEL[3:0]

options, the analog input muxing section must be configured

manually to correctly route the video from the analog

input pins to the ADC. The standard definition processor

block, which decodes the digital data, must be configured

to process the CVBS, Y/C, or YPrPb format. This is performed

by INSEL[3:0] selection.

CONNECT ANALOG VIDEO

SIGNALS TO ADV7180.

SET INSEL[3:0] TO CONFIGURE

VIDEO FORMAT. USE PREDEFINED

FORMAT/ROUTING.

CONFIGURE ADC INPUTS USING

MANUAL MUXING CONTROL BITS:

MUX_0[2:0], MUX_1[2:0], MUX_2[2:0].

SEE TABLE 15.

REFER TO

TABLE 13

REFER TO

TABLE 14

LQFP-64

LQFP-48

LFCSP-40

LFCSP-32

05700-011

YES

Figure 16. Signal Routing Options

INSEL[3:0], Input Selection, Address 0x00[3:0]

The INSEL bits allow the user to select the input format. They

also configure the standard definition processor core to process

composite (CVBS), S-Video (Y/C), or component (YPrPb) format.

INSEL[3:0] has predefined analog input routing schemes that

do not require manual mux programming (see Table 13 and

Table 14). This allows the user to route the various video signal

types to the decoder and select them using INSEL[3:0] only.

The added benefit is that if, for example, the CVBS input is

selected, the remaining channels are powered down.

Table 13. 64-Lead and 48-Lead LQFP INSEL[3:0]

INSEL[3:0] Video Format Analog Input

0000 Composite CVBS input on A

0001 Composite CVBS input on A

0010 Composite CVBS input on A

0011 Composite CVBS input on A

0100 Composite CVBS input on A

0101 Composite CVBS input on A

0110 Y/C (S-Video) Y input on A

C input on A

0111 Y/C (S-Video) Y input on A

C input on A

1000 Y/C (S-Video) Y input on A

C input on A

1001 YPrPb Y input on A

Pb input on A

Pr input on A

1010 YPrPb Y input on A

Pr input on A

Pb input on A

1011 to 1111 Reserved Reserved

Table 14. 40-Lead and 32-Lead LFCSP INSEL[3:0]

INSEL[3:0] Video Format Analog Input

0000 Composite CVBS input on A

0001 to 0010 Reserved Reserved

0011 Composite CVBS input on A

0100 Composite CVBS input on A

0101 Reserved Reserved

0110 Y/C (S-Video) Y input on A

C input on A

0111 to 1000 Reserved Reserved

1001 YPrPb Y input on A

Pr input on A

Pb input on A

1010 to 1111 Reserved Reserved

剩余115页未读，继续阅读

tanzhongqiang1113

粉丝: 0
资源: 1

ADV7180: 10-Bit SDTV Video Decoder with Auto NTSC/PAL/SECAM Supp...

最新资源

ADV7180: 10-Bit SDTV Video Decoder with Auto NTSC/PAL/SECAM Supp...

adv7180 芯片手册

ADV7180 视频解码器

hi3516a adv7180驱动代码

ir adv 4051-4045-4035-4025 series

apt-key adv --keyserver

adv7180芯片作用

如何使用ADV7280-M芯片将CVBS信号转换为MIPI CSI-2接口的视频数据流？请提供具体的硬件连接和软件编程步骤。

sudo apt-key adv --fetch-keys https://developer.download.nvidia.com/compute/cuda/repos/ubuntu1804/x86_64/7fa2af80.pub

最后的参数为上述出现的NO_PUBKEY对应的参数后八位，共两个sudo apt-get adv --recv-key --keyserver keyserver.Ubuntu.com 437

esd adv11.2-1995 中文版

最新资源