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首页MFRC522:NFC卡片读写器操作手册(ISO14443A/MIFARE兼容)
MFRC522:NFC卡片读写器操作手册(ISO14443A/MIFARE兼容)
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更新于2024-07-16
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"MFRC522.pdf"文档是关于NFC卡读卡器/写卡器MFRC522的详细介绍,该芯片专为13.56 MHz无接触通信设计,支持ISO 14443A/MIFARE®协议。它具有高度集成的特性,包括内置发射器部分,能够驱动一个与ISO/IEC 14443A/MIFARE®卡片和应答器通信的天线,无需额外的主动电路。接收器部分则提供了对来自兼容卡片和应答器信号的强大且高效的解调和解码能力,包括ISO/IEC 14443A帧结构和错误检测(奇偶校验和CRC)。 MFRC522特别支持MIFARE® Classic系列,如MIFARE®标准,能够在双向通信中实现高达848 kbit/s的高速非接触传输。文档还涵盖了多种主机接口选项: 1. SPI接口:这是一种串行外设接口,适用于需要直接与微控制器交互的场合,提供高效的数据传输。 2. 串行UART:类似于RS-232标准,但电压水平根据电源供应调整,是一种通用的通信方式,适用于对数据通信速率要求不高的应用。 3. I2C接口:这是一种串行总线接口,适合于多个设备共享数据线的情况,简化了硬件连接和管理。 在学习和操作MFRC522时,这份文档是不可或缺的指南,不仅包含了芯片的工作原理、功能规格,还有详细的接口操作说明,有助于开发者理解和实现基于NFC技术的项目,无论是卡片读取、数据交换还是系统集成,都能从中找到所需的信息。对于希望通过MFRC522进行NFC开发的人来说,无论是硬件设计还是软件编程,都需要深入阅读并掌握其中的内容。
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112132 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 3.2 — 22 May 2007 16 of 109
NXP Semiconductors
MFRC522
Contactless Reader IC
9.2.1.4 DivIEnReg
Control bits to enable and disable the passing of interrupt requests.
9.2.1.5 CommIRqReg
Contains Interrupt Request bits.
Table 13: DivIEnReg register (address 03h); reset value: 00h
Bit 7 6 5 4 3 2 1 0
Symbol IRQPushPull - MfinActIEn - CRCIEn -
Access
Rights
r/w RFU r/w RFU r/w RFU
Table 14: Description of DivIEnReg bits
Bit Symbol Description
7 IRQPushPull Set to logic 1, the pin IRQ works as standard CMOS output pad.
Set to logic 0, the pin IRQ works as open drain output pad.
6 to 5 - Reserved for future use.
4 MfinActIEn Allows the MFIN active interrupt request to be propagated to pin IRQ.
3 - Reserved for future use.
2 CRCIEn Allows the CRC interrupt request (indicated by bit CRCIRq) to be
propagated to pin IRQ.
1 to 0 - Reserved for future use.
Table 15: CommIRqReg register (address 04h); reset value: 14h
Bit 7 6 5 4 3 2 1 0
Symbol Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq
Access
Rights
wdydydy dy dy dydy
Table 16: Description of CommIRqReg bits
All bits in the register CommIRqReg shall be cleared by software.
Bit Symbol Description
7 Set1 Set to logic 1, Set1 defines that the marked bits in the register CommIRqReg
are set.
Set to logic 0, Set1 defines, that the marked bits in the register CommIRqReg
are cleared.
6 TxIRq Set to logic 1 immediately after the last bit of the transmitted data was sent out.
5 RxIRq Set to logic 1 when the receiver detects the end of a valid data stream.
If the bit RxNoErr in register RxModeReg is set to logic 1, Bit RxIRq is only set
to logic 1 when data bytes are available in the FIFO.
4 IdleIRq Set to logic 1, when a command terminates by itself e.g. when the
CommandReg changes its value from any command to the Idle Command.
If an unknown command is started, the CommandReg changes its content to
the idle state and the bit IdleIRq is set. Starting the Idle Command by the
μ-Controller does not set bit IdleIRq.
3 HiAlertIRq Set to logic 1, when bit HiAlert in register Status1Reg is set. In opposition to
HiAlert, HiAlertIRq stores this event and can only be reset as indicated by bit
Set1.
![](https://csdnimg.cn/release/download_crawler_static/11775720/bg11.jpg)
112132 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 3.2 — 22 May 2007 17 of 109
NXP Semiconductors
MFRC522
Contactless Reader IC
9.2.1.6 DivIRqReg
Contains Interrupt Request bits
2 LoAlertIRq Set to logic 1, when bit LoAlert in register Status1Reg is set. In opposition to
LoAlert, LoAlertIRq stores this event and can only be reset as indicated by bit
Set1.
1 ErrIRq Set to logic 1 if any error bit in the ErrorReg Register is set.
0 TimerIRq Set to logic 1 when the timer decrements the TimerValue Register to zero.
Table 16: Description of CommIRqReg bits
…continued
All bits in the register CommIRqReg shall be cleared by software.
Bit Symbol Description
Table 17: DivIRqReg register (address 05h); reset value: X0h
Bit 7 6 5 4 3 2 1 0
Symbol Set2 - MfinActIRq - CRCIRq -
Access
Rights
wRFU dyRFUdy RFU
Table 18: Description of DivIRqReg bits
All bits in the register DivIRqReg shall be cleared by software.
Bit Symbol Description
7 Set2 Set to logic 1, Set2 defines that the marked bits in the register
DivIRqReg are set.
Set to logic 0, Set2 defines, that the marked bits in the register
DivIRqReg are cleared
6 to 5 - Reserved for future use.
4 MfinActIRq Set to logic 1, when MFIN is active. This interrupt is set when either a
rising or falling signal edge is detected.
3 - Reserved for future use.
2 CRCIRq Set to logic 1, when the CRC command is active and all data are
processed.
1 to 0 - Reserved for future use.
![](https://csdnimg.cn/release/download_crawler_static/11775720/bg12.jpg)
112132 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 3.2 — 22 May 2007 18 of 109
NXP Semiconductors
MFRC522
Contactless Reader IC
9.2.1.7 ErrorReg
Error bit register showing the error status of the last command executed.
[1] Command execution will clear all error bits except for bit TempErr. A setting by software is impossible.
Table 19: ErrorReg register (address 06h); reset value: 00h
Bit 7 6 5 4 3 2 1 0
Symbol WrErr TempErr - BufferOvfl CollErr CRCErr ParityErr ProtocolErr
Access
Rights
rrRFUr rrr r
Table 20: Description of ErrorReg bits
Bit Symbol Description
7 WrErr Set to logic 1, when data is written into the FIFO by the host during the
MFAuthent command or if data is written into the FIFO by the host
during the time between sending the last bit on the RF interface and
receiving the last bit on the RF interface.
6 TempErr
[1]
Set to logic 1, if the internal temperature sensor detects overheating.
In this case, the antenna drivers are switched off automatically.
5 - Reserved for future use.
4 BufferOvfl Set to logic 1, if the host or a MFRC522’s internal state machine (e.g.
receiver) tries to write data into the FIFO buffer although the FIFO
buffer is already full.
3 CollErr Set to logic 1, if a bit-collision is detected. It is cleared automatically at
receiver start-up phase. This bit is only valid during the bitwise
anticollision at 106 kbit/s. During communication schemes at 212,
424 and 848 kbit/s this bit is always set to logic 0.
2 CRCErr Set to logic 1, if bit RxCRCEn in register RxModeReg is set and the
CRC calculation fails. It is cleared to logic 0 automatically at receiver
start-up phase.
1 ParityErr Set to logic 1, if the parity check has failed. It is cleared automatically
at receiver start-up phase. Only valid for ISO/IEC 14443A/MIFARE
®
communication at 106 kbit/s.
0 ProtocolErr Set to logic 1, if one out of the following cases occur:
• Set to logic 1 if the SOF is incorrect. It is cleared automatically at
receiver start-up phase. The bit is only valid for 106 kbit/s.
• During the MFAuthent Command, bit ProtocolErr is set to logic 1,
if the number of bytes received in one data stream is incorrect.
![](https://csdnimg.cn/release/download_crawler_static/11775720/bg13.jpg)
112132 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 3.2 — 22 May 2007 19 of 109
NXP Semiconductors
MFRC522
Contactless Reader IC
9.2.1.8 Status1Reg
Contains status bits of the CRC, Interrupt and FIFO buffer.
Table 21: Status1Reg register (address 07h); reset value: 21h
Bit 7 6 5 4 3 2 1 0
Symbol - CRCOk CRCReady IRq TRunning - HiAlert LoAlert
Access
Rights
RFU r r r r RFU r r
Table 22: Description of Status1Reg bits
Bit Symbol Description
7 - Reserved for future use.
6 CRCOk Set to logic 1, if the CRC result is zero. For data transmission and
reception the bit CRCOk is undefined (use CRCErr in register
ErrorReg). CRCOk indicates the status of the CRC co-processor,
during calculation the value changes to logic 0, when the calculation is
done correctly, the value changes to logic 1.
5 CRCReady Set to logic 1, when the CRC calculation has finished. This bit is only
valid for the CRC co-processor calculation using the command
CalcCRC.
4 IRq This bit shows, if any interrupt source requests attention (with respect
to the setting of the interrupt enable bits, see register CommIEnReg
and DivIEnReg).
3 TRunning Set to logic 1, if the MFRC522’s timer unit is running, e.g. the timer will
decrement the TCounterValReg with the next timer clock.
Remark: In the gated mode the bit TRunning is set to logic 1, when
the timer is enabled by the register bits. This bit is not
influenced by the gated signal.
2 - Reserved for future use.
1 HiAlert Set to logic 1, when the number of bytes stored in the FIFO buffer
fulfils the following equation:
Example:
FIFOLength = 60, WaterLevel = 4 → HiAlert = 1
FIFOLength = 59, WaterLevel = 4 → HiAlert = 0
0 LoAlert Set to logic 1, when the number of bytes stored in the FIFO buffer
fulfils the following equation:
Example:
FIFOLength = 4, WaterLevel = 4 → LoAlert = 1
FIFOLength = 5, WaterLevel = 4 → LoAlert = 0
HiAlert 64 FIFOLength– )( WaterLevel≤=
LoAlert FIFOLength WaterLevel≤=
![](https://csdnimg.cn/release/download_crawler_static/11775720/bg14.jpg)
112132 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 3.2 — 22 May 2007 20 of 109
NXP Semiconductors
MFRC522
Contactless Reader IC
9.2.1.9 Status2Reg
Contains status bits of the receiver, transmitter and data mode detector.
Table 23: Status2Reg register (address 08h); reset value: 00h
Bit 7 6 5 4 3 2 1 0
Symbol TempSens
Clear
I
2
CForceHS - MFCrypto1On Modem State
Access
Rights
r/w r/w RFU dy r
Table 24: Description of Status2Reg bits
Bit Symbol Description
7 TempSensClear Set to logic 1, this bit clears the temperature error, if the temperature
is below the alarm limit of 125 °C.
6I
2
CForceHS I
2
C input filter settings.
Set to logic 1, the I
2
C input filter is set to the High-speed mode
independent of the I
2
C protocol.
Set to logic 0, the I
2
C input filter is set to the used I
2
C protocol.
5 to 4 - Reserved for future use.
3 MFCrypto1On This bit indicates that the MIFARE
®
Crypto1 unit is switched on and
therefore all data communication with the card is encrypted.
This bit can only be set to logic 1 by a successful execution of the
MFAuthent Command. This bit is only valid in Reader/Writer mode
for MIFARE
®
Standard cards. This bit shall be cleared by software.
2 to 0 Modem State ModemState shows the state of the transmitter and receiver state
machines.
Status Description
000 IDLE
001 Wait for bit StartSend in register BitFramingReg
010 TxWait: Wait until Rf field is present, if the bit TxWaitRF is set
to logic 1. The minimum time for TxWait is defined by the
TxWaitReg register.
011 Transmitting
100 RxWait: Wait until RF field is present, if the bit RxWaitRF is
set to logic 1. The minimum time for RxWait is defined by the
RxWaitReg register.
101 Wait for data
110 Receiving
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