FPGA架构上的高性能整数算术电路设计与优化

需积分: 10 201 浏览量更新于2024-07-17 1 收藏 5.43MB PDF 举报

"《High Performance Integer Arithmetic Circuit Design on FPGA Architecture》是 Springer Series in Advanced Microelectronics 系列第51卷的一本书，由Ayan Palchaudhuri和Rajat Subhra Chakraborty撰写。该书深入探讨了在FPGA架构上优化实现整数算术数据路径、控制路径和伪随机序列生成器电路的方法。书中通过在HDL规范中直接实例化目标FPGA特定原语，研究了常规、模块化、级联和位切片架构。作者使用详细的数学分析来证明每种提议架构的合理性，并通过约束布局来提高性能，将逻辑相关的硬件原语紧密放置在一起，从而最小化路由延迟。这通过向Xilinx专有的‘用户约束文件’(.ucf)提供相关约束来实现，以便于FPGA CAD工具进行布局。" 在本书中，读者可以了解到以下关键知识点： 1. **FPGA架构**：FPGA（Field-Programmable Gate Array）是一种可编程的集成电路，允许设计者根据需求定制硬件功能。书中详细讨论了如何利用FPGA的灵活性和可配置性来优化整数算术电路。 2. **整数算术电路**：这些电路包括加法器、减法器、乘法器等，是数字系统的基础组件。优化这些电路对于提升计算速度和效率至关重要。 3. **数据路径与控制路径**：数据路径处理计算操作，而控制路径管理操作的顺序和条件。书中的内容可能涵盖了如何在FPGA上高效实现这两部分。 4. **模块化与级联架构**：模块化设计允许将复杂电路分解为可复用的单元，级联架构则通过连接多个基本模块来扩展功能。这两种方法有助于减少设计时间和提高设计的可维护性。 5. **位切片技术**：位切片是一种将电路设计为处理多位数据的并行方式，它能够显著提高运算速度，尤其在处理大量数据时。 6. **硬件描述语言（HDL）**：HDL如VHDL或Verilog用于描述数字系统的逻辑行为。书中说明了如何直接在HDL中实例化FPGA特定的原语。 7. **约束驱动布局**：通过在UCF文件中设置约束，设计者可以指导布局工具进行更有效的物理布局，以减少布线延迟，提高系统性能。 8. **伪随机序列生成器**：这类电路在加密、测试和仿真等多个领域有广泛应用。书中可能探讨了如何在FPGA上实现高效和安全的伪随机序列生成。 9. **性能分析与优化**：作者通过详细的数学分析来评估和改进电路性能，这种分析可能涉及了延迟、功耗和面积等方面的考量。 10. **CAD工具集成**：与Xilinx的FPGA CAD工具（如ISE或Vivado）的集成，使设计流程更加自动化和高效。《High Performance Integer Arithmetic Circuit Design on FPGA Architecture》为读者提供了关于FPGA上高性能整数算术电路设计的深入理解和实践指导，对于电子工程师和研究人员来说，是一本宝贵的参考资源。

Chapter 1

Introduction

Abstract This chapter presents a concise overview of FPGA-based architecture

design. Certain existing research work behind proposing new FPGA architectures

and CAD heuristics to overcome the design limitations have been discussed. It also

unfolds the limitations of the FPGA CAD tool that are currently popular for arith-

metic core generation. A methodology that uses the target FPGA speciﬁc primitive

instantiation-based approach and constrained placement exercise has been proposed

as a superior alternative in comparison to design implementations available in liter-

ature. The major contributions of this book have also been listed.

1.1 Background of FPGA-Based Design

Researchers over the years have proposed various Field Programmable Gate Array

(FPGA) architectures for high performance realization of digital circuits, particularly

those that have long cascading delay, e.g., ripple carry adder. In [19], an enhanced cas-

cade circuit with dedicated routing structures for fast propagation of signals between

cells was proposed to achieve a signiﬁcant speedup. In [11], the authors had con-

sidered a folding method of logic functions and its adaptation to map to proposed

Look-Up Table (LUT) architectures, such that the memory requirement for real-

ization of the logic functions can be signiﬁcantly reduced. It has also been studied

that reducing the number of stages of programmable routing (e.g., routing through

switchboxes) can signiﬁcantly reduce the critical path [17]. This can be achieved

through use of LUTs which support maximum functionality and dedicated routing

along with other logic blocks. Experiments have conﬁrmed that 6-input LUTs pro-

vide the right trade-off between critical path delay and design die size [3]. With

culmination of all such similar research paradigms, modern FPGAs have architec-

tural features amenable to the efﬁcient implementation of combinational functions

of arbitrary complexity in the form of LUTs, along with fast special-purpose logic

and routing resources for propagating carry signals between adjacent logic blocks

in form of carry chain [9].

However, with a signiﬁcant increase in circuit complexity for FPGA-based

designs, even the most sophisticated Computer Aided Design (CAD) tools often

result in circuit implementations with unsatisfactory performance and resource

A. Palchaudhuri and R.S. Chakraborty, High Performance Integer Arithmetic

Circuit Design on FPGA, Springer Series in Advanced Microelectronics 51,

DOI 10.1007/978-81-322-2520-1_1

2 1 Introduction

requirements owing to their inability to optimally exploit the underlying FPGA

architecture and their dedicated routing fabric. Hence, implementations derived

through the standard automatic logic synthesis-based design ﬂow starting with the

behavioral Hardware Description Language (HDL) as the mode of design entry of the

circuit, can be outperformed by more low-level “custom” design techniques. Exten-

sive experimentation with the Xilinx FPGA CAD tool has shown that though the tool

is able to infer the desired hardware primitives for many combinational logic circuits,

it generally fails to do so when we synthesize sequential or pipelined architectures.

In addition, the current FPGA CAD tools often fail to place the technology mapped

sub-circuits at locations such that circuit delay is minimized. To overcome these lim-

itations, a designer needs to identify the basic building blocks of the required circuit,

and make an effort to optimally construct them from the hardware primitives avail-

able on the FPGA and ensure their proper placement. This book discusses several

FPGA-speciﬁc design techniques that need to be adopted for optimal realization of

high performance circuits and presents relevant case studies.

The rest of the chapter is organized as follows. In Sect. 1.2, we discuss the limita-

tions of FPGA CAD tools for realization of high performance circuits. In Sect. 1.3,

we describe the design philosophy that must be adopted to overcome the limitations

posed by current FPGA CAD tools. Section 1.4 discusses two popular FPGA CAD

tools—the standard Xilinx Integrated Software Environment (ISE)-based Graphical

User Interface (GUI) for IP Core Generator and FloPoCo (in short for Floating–Point

Cores) where user inputs circuit speciﬁcations and the CAD tool generates the cor-

responding synthesizable HDL speciﬁcation of the circuit. In Sect. 1.5, we mention

some of the recent works on architectural realization of arithmetic circuits on Xilinx

FPGAs. We state the major contributions of this book in Sect. 1.6. The organization

of the book is presented in Sect. 1.7.

1.2 Limitations of FPGA CAD Tools

Modern CAD tools for FPGA platform facilitate the automatic mapping of binary

addition logic to carry-chain structures to accelerate signal propagation, thereby

achieving a speedup in the critical paths. In addition, existence of carry-chain simpli-

ﬁes routing by avoiding switch-boxes in the general routing fabric, and also increases

the functional capability of the FPGA logic slices. Such beneﬁts have been experi-

mentally evaluated on the basis of combinational MCNC benchmarks in [15]. Though

synthesis tools for Xilinx Virtex architectures are able to map the binary addition

logic or a homogeneous wide AND and OR gates to carry chain fabric [16], or can

infer the wide function multiplexers native to an FPGA slice, it fails to do so as soon

as the ﬁnal carry outputs of individual slices [14] or intermediate LUT outputs are

tapped out or registered to facilitate pipelining of the architecture. A possible rea-

son might be that Xilinx FPGA logic slices do not support dedicated hardware for

registering such signals, and the CAD tools fail to infer the desired implementation.

In such a scenario, the designer has to spell out special directives in the HDL of

1.2 Limitations of FPGA CAD Tools 3

the design or associated “constraints ﬁles” to the FPGA CAD tool, so that in the

packing [1]orclustering step (as known in the FPGA CAD literature) of the FPGA

design ﬂow, the technology mapped circuit is efﬁciently “packed” into the available

hardware resources.

1.3 Overview of Design Philosophy for FPGAs

Most current FPGA vendors allow direct instantiation of the available primitives in

the HDL code [21], and a “mixed” style of HDL coding, where high-level behavioral

code is intermingled with relatively “low-level” structural code. Placement steps

also need to be constrained and controlled, as the CAD placement tools, if allowed

to perform unconstrained placement and routing, often result in large routing delays.

This happens because the technology mapped logic elements get unevenly distrib-

uted across the FPGA fabric, resulting in greater routing and interconnect delays.

This contributes to a major portion of the circuit critical path delay. Although most

modern FPGA vendors provide special hardware IPs for common integer arithmetic

operations which can be directly instantiated in the HDL code, we would demonstrate

that we can do better by adopting careful design techniques.

To follow the methodology promoted above, the designer must possess a thorough

understanding of the target FPGA architecture, the routing fabric, the available design

elements in the form of primitives and macros, and how t o conﬁgure them to achieve

the required functionality. Also, the s tructure of the circuits must have sufﬁcient

regularity to automate their design, and to allow efﬁcient placement and routing.

Arithmetic circuits and Finite State Machines (FSMs) with regular structures (e.g.,

counters and shift registers) are thus the ideal candidates for this methodology.

1.3.1 Target FPGA-Speciﬁc Hardware Primitive Instantiation

With sufﬁcient modularity in the circuit architecture, it becomes easy to automate

the generation of the HDL code, and associated constraint ﬁles which are themselves

very regular in their grammar. Target FPGA-speciﬁc primitive instantiation is an

effective approach for optimization of designs on the Xilinx FPGA platform [7],

and is often the only approach. The primitive instantiation-based methodology is

also simpler than rewriting the Register Transfer Level (RTL) code to coax the logic

synthesis tool to infer the desired architectural components. However, in general,

the entire circuit might not be amenable to the primitive instantiation-based design

approach. In such cases, this approach can be adopted to design only those parts of

the circuit that are amenable to such a methodology, and contribute signiﬁcantly to

the critical path delay. The only disadvantage of using such a design methodology

is that the design becomes less portable, and becomes harder to maintain. In s pite of

this, the methodology is very effective in practice, considering the facts that (a) often

4 1 Introduction

the target FPGA platform is known before the circuit is designed and that (b) FPGAs

from a related family from the same vendor are often backward compatible regarding

the design elements (primitives and macros) supported. For example, newer versions

of FPGAs of the “Virtex” family from Xilinx are expected to support primitives

supported in some older Virtex versions. Thus, the HDL code for instantiating prim-

itives targeting the older versions, and the constraints ﬁle to control the placement,

can be reused in the newer version after small tweaks, if necessary. Added with the

advantage of being able to automatically generate the circuit descriptions and the

constraints, this is an attractive methodology.

1.4 Existing FPGA CAD Tools

The most popular FPGA CAD tools for arithmetic core generation are the Xilinx IP

Core Generator and an open source tool called FloPoCo. We brieﬂy describe their

main features and the relevant shortcomings.

1.4.1 Xilinx IP Core Generator

The Xilinx IP Core Generator is part of the standard Xilinx ISE distribution, It

includes a GUI-based utility, through which synthesizable HDL code (for common

integer arithmetic circuits such as adders, multipliers, accumulators, counters, etc.)

can be automatically generated. Designers can generate both combinational and

pipelined versions of the arithmetic circuits, where the user enters the parameter

latency as input for pipelined architecture realizations. Although such HDL auto-

matically generated by the Xilinx software is functionally correct, it fails to give

high performance when implemented, because the synthesis tool performs an inefﬁ-

cient technology mapping of the circuit, and the inferred logic elements are usually

scattered in an apparently random fashion across the FPGA fabric, thereby causing

large routing delays and affecting critical paths. Xilinx also allows the direct instan-

tiation of “Digital Signal Processing” (DSP) hardware macros in the HDL targeted

for FPGAs, which are highly customized dedicated arithmetic circuits. Individual

Virtex-5 DSP slices can operate at a maximum frequency of 550 MHz [20], Virtex-6

DSP slices can operate at a maximum frequency of 600MHz [22]; such operating

frequencies are attainable at very low latency and are also suitable for low power

applications. However, as we would demonstrate, they have performance limitations

for large operand widths, and can be outperformed by the proposed circuits with

aggressive pipelining, coupled with compact and constrained placement of logic

primitives.

1.4 Existing FPGA CAD Tools 5

1.4.2 FloPoCo (Floating-Point Cores)

FloPoCo is an open-source C++ framework for generating arithmetic cores for

FPGAs [8]. FloPoCo provides a command-line interface through which the user can

input operator speciﬁcations, and the program generates the corresponding synthe-

sizable VHDL (Very High Speed Integrated Circuit Hardware Description Language)

code. The main features of FloPoCo as listed in [6] are as follows:

• Supports integer, ﬁxed point, ﬂoating point, and Logarithmic Number System

(LNS) arithmetic.

• Supports pipelining by allowing the user to specify the desired operating frequency.

• Allows the user to specify the target FPGA implementation platform, and generates

synthesizable VHDL code optimized for that target platform. In addition, FloPoCo

performs target platform-speciﬁc pipelining, as its frequency-directed pipelining

takes into consideration the timing information about the target FPGA platform [6].

FloPoCo comes with such models for the main FPGA families from both Xilinx

and Altera.

However, detailed experimentation with the latest released version of FloPoCo

(v 2.5.0) [8], and implementation and characterization of the integer arithmetic circuit

descriptions generated by it indicate the following drawbacks:

• FloPoCo only generates pure behavioral VHDL code which cannot correctly infer

the desired hardware primitives of the target FPGA platform. Consequently, it has

no control over the inference and placement of logic blocks on the FPGA fabric.

This makes the performance of the circuit post-synthesis worse than the target

frequency speciﬁed by the user. Thus, FloPoCo provides no guarantee that the

target frequency speciﬁed would be met in the ﬁnal implementation.

• FloPoCo at times create very deep pipelines, apparently to meet input frequency

constraints, but post place-and-route implementations do not guarantee that the

delay constraints are met.

• Pipelining behavior of FloPoCo is very inconsistent. It was observed t hat for adder

circuit implementations, FloPoCo creates very deep pipelines, whereas it cre-

ates fairly unbalanced and irregular pipelines for dual subtractor implementations,

where each of the pipeline stages have different complexities. On the contrary, it

completely avoids pipelining the integer multipliers, but, however, generates an

erroneous comment in the VHDL code that it has achieved single stage pipelining.

Similar observations have been made for the squarer circuits where FloPoCo is

unable to pipeline squarer circuits whose input operand bit-widths are lower than

14, but create highly inefﬁcient pipelines for squarer circuits of higher bit-widths.

Our observations about these inconsistencies in the pipelining behavior of the cur-

rent version of FloPoCo have been concurred with by the creators of FloPoCo

through personal correspondence. They have acknowledged that a bug exists in

their program, which they have ﬁled and would probably be taken care of in future

releases.

剩余124页未读，继续阅读

zongzongzong1

粉丝: 10
资源: 8

FPGA架构上的高性能整数算术电路设计与优化

FPGA Placement Methodologies

On the design of high performance digital arithmetic units

根升余弦脉冲成形滤波器FPGA实现.pdf

基于DA算法的FIR数字滤波器的FPGA设计.pdf

基于分布式算法的FIR滤波器设计及FPGA实现.pdf

基于分布式算法的高阶FIR滤波器及其FPGA实现.pdf

基于HEVC的CABAC二进制算术编码器的FPGA实现.pdf

基于查阶跃响应表的高效FIR滤波器设计及其FPGA实现.pdf

Distributed-Arithmetic-Based DLMS Adaptive Filter on FPGA_Chenhui_Qiu.pdf

GTM007 A Course in Arithmetic, J.P.Serre, Springer 1973.pdf

最新资源