Why migrate from STM32F10xxx FWLib V2.0.3 to StdPeriph_Lib V3.0.0? AN2953
6/33 Doc ID 15531 Rev 1
1 Why migrate from STM32F10xxx FWLib V2.0.3 to
StdPeriph_Lib V3.0.0?
The STM32F10xxx FWLib V2.0.3 is a complete firmware package for the STM32F10xxx
low-, medium- and high-density devices. It is a collection of routines, data structures and
macros that covers the features of all peripherals. It includes drivers and a set of examples
for all the standard device peripherals.
The STM32F10xxx StdPeriph_Lib V3.0.0 is an update of FWLib V2.0.3:
● It makes the library compliant with the Cortex™ microcontroller software interface
standard (CMSIS)
● the package architecture has been enhanced
● the source files are provided in the Doxygen format
● the update has no impact on the STM32 peripheral drivers’ API (application
programming interface)
Note: Only the STM32F10xxx CAN driver was updated to anticipate the support of STM32F10xxx
connectivity line products (products with dual CAN).
To migrate to the STM32F10xxx standard peripheral library V3.0.0, you simply have to
update the:
● files relative to your toolchain
● project setting
● library file organization
● you do not need to change or update the application code
The details of all updates made on the library (StdPeriph_Lib) are described below.
1.1 ARM
®
Cortex-M3™ microcontroller software interface
standard (CMSIS) compliance
The CMSIS answers the challenges faced when software components are deployed to
physical microcontroller devices based on Cortex-M0 / Cortex-M1 or Cortex-M3 processors.
The CMSIS will also be expanded to future Cortex-M processor cores (the standard refers to
Cortex-Mx). The CMSIS is defined in close cooperation with various silicon and software
vendors and provides a common approach to interface to peripherals, real-time operating
systems and middleware components. For more details, please refer to www.onarm.com.
1.1.1 CMSIS description
As part of the CMSIS, ARM provides the following software layers, which are available for
various compiler implementations:
● Core peripheral access layer: contains name definitions, address definitions and
helper functions to access core registers and peripherals. It also defines a device-
independent interface for RTOS Kernels that includes debug channel definitions.
● Middleware access layer: provides common methods to access peripherals for the
software industry. The middleware access layer is adapted by the Silicon vendor to the
device-specific peripherals used by the middleware components. The middleware
access layer is currently in development and not yet part of this documentation.
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