P25Q40U/20U/10U/05U Datasheet
Puya Semiconductor Page 13 of 75
5.5 Operation Conditions
At Device Power-Up and Power-Down
AC timing illustrated in "Figure AC Timing at Device Power-Up" and "Figure Power-Down Sequence" are for
the supply voltages and the control signals at device power-up and power-down. If the timing in the figures is
ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to
be selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 5-8 AC Timing at Device Power-Up
SCLK
SI
CS#
MSB
SO
tDVCH
High-Z
LSB
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSH tCHSL
tVR
VCC
VCC(min)
GND
Figure 5-9 Power-up Timing
Vcc(max)
Vcc(min)
VWI
tVSL
Chip Selection is not allowed
Device is fully accessible
Time
剩余74页未读，继续阅读
