AM335X：1GHz ARM Cortex-A8 处理器技术详解

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"AM335X.pdf 是一份关于德州仪器（TI）的AM335x Sitara系列微处理器的详细技术文档。该处理器基于ARM Cortex-A8 32位RISC架构，具备高性能计算能力，适用于各种嵌入式应用。主要特性包括： 1. **处理器核心**：AM335x集成1GHz的ARM Cortex-A8内核，支持NEON SIMD协处理器，提供高效的多媒体处理能力。 2. **内存系统**：拥有32KB的L1指令缓存和32KB的L1数据缓存，两者都配备单位检错（奇偶校验）功能，确保数据完整性。此外，还包括256KB带ECC的L2缓存，减少错误并提高稳定性。 3. **启动与安全**：176KB的片载启动ROM用于存储固件，64KB的专用RAM用于应用程序运行，JTAG接口则用于仿真和调试。 4. **中断管理**：强大的中断控制器能处理多达128个中断请求，便于实时系统管理。 5. **片上存储**：64KB的通用片上存储器控制器（OCMC）RAM，可被所有主机访问，支持快速唤醒功能，增强了系统的响应速度。 6. **外部存储接口**：AM335x支持多种类型的外部存储器，如mDDR、DDR2、DDR3和DDR3L，提供不同速率的数据传输，并允许1GB的全部寻址空间。此外，通用存储器控制器（GPMC）提供对8位和16位异步存储器的灵活接口，兼容多种类型的非易失性存储器。 7. **错误纠正**：通过BCH代码支持对4位、8位或16位错误的纠正，提高了数据存储的可靠性。 8. **安全性与认证**：文档特别提到，产品数据适用于生产，且在安全关键应用中的使用需谨慎，涉及知识产权和免责声明。 9. **文档链接**：可以访问相关的技术文档、工具软件、支持社区以及参考设计。 AM335x处理器的这些特性使其在嵌入式领域，特别是在需要高效能、低功耗、可靠性和灵活性的应用中表现出色，如工业自动化、物联网设备、消费电子和汽车电子等领域。"

Middle
Pin map section location
16
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
ZHCS488J –OCTOBER 2011–REVISED APRIL 2016
www.ti.com.cn
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Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351
Terminal Configuration and Functions Copyright © 2011–2016, Texas Instruments Incorporated
ZCZ Pin Map [Section Middle - Top View]
G H J K L M
18 MMC0_CMD RMII1_REF_CLK MII1_TXD3 MII1_TX_CLK MII1_RX_CLK MDC
17 MMC0_CLK MII1_CRS MII1_RX_DV MII1_TXD0 MII1_RXD3 MDIO
16 MMC0_DAT0 MII1_COL MII1_TX_EN MII1_TXD1 MII1_RXD2 MII1_RXD0
15 MMC0_DAT1 VDDS_PLL_MPU MII1_RX_ER MII1_TXD2 MII1_RXD1 USB0_CE
14 VDDSHV6 VDDSHV4 VDDSHV4 VDDSHV5 VDDSHV5 VSSA_USB
13 VDD_MPU VDD_MPU VDD_MPU VDDS VSS VDD_CORE
12 VSS VSS VDD_CORE VDD_CORE VSS VSS
11 VSS VDD_CORE VSS VSS VSS VDD_CORE
10 VDD_CORE VSS VSS VSS VSS VSS
9 VSS VSS VSS VSS VDD_CORE VSS
8 VSS VSS VSS VDD_CORE VDD_CORE VSS
7 VDD_CORE VSS VSS VSS VDD_CORE VSS
6 VDD_CORE VSS VSS VDD_CORE VDD_CORE VSS
5 VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VPP
4 DDR_RASn DDR_A14 DDR_VREF DDR_D12 DDR_D14 DDR_D1
3 DDR_CKE DDR_A13 DDR_VTP DDR_D11 DDR_D13 DDR_D0
2 DDR_RESETn DDR_CSn0 DDR_DQM1 DDR_D10 DDR_DQSn1 DDR_DQM0
1 DDR_ODT DDR_A1 DDR_D8 DDR_D9 DDR_DQS1 DDR_D15

AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351

ZHCS488J –OCTOBER 2011–REVISED APRIL 2016

www.ti.com.cn

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Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

4.2 Pin Attributes

The AM335x and AMIC110 Sitara Processors Technical Reference Manual and this document may

reference internal signal names when discussing peripheral input and output signals because many of the

AM335x package terminals can be multiplexed to one of several peripheral signals. The following table

has a Pin Name column that lists all device terminal names and a Signal Name column that lists all

internal signal names multiplexed to each terminal which provides a cross reference of internal signal

names to terminal names. This table also identifies other important terminal characteristics.

1. BALL NUMBER: Package ball numbers associated with each signals.

2. PIN NAME: The name of the package pin or terminal.

Note: The table does not take into account subsystem terminal multiplexing options.

3. SIGNAL NAME: The signal name for that pin in the mode being used.

4. MODE: Multiplexing mode number.

a. Mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the

terminal corresponds to the name of the terminal. There is always a function mapped on the

primary mode. Notice that primary mode is not necessarily the default mode.

Note: The default mode is the mode at the release of the reset; also see the RESET REL. MODE

column.

b. Modes 1 to 7 are possible modes for alternate functions. On each terminal, some modes are

effectively used for alternate functions, while some modes are not used and do not correspond to a

functional configuration.

5. TYPE: Signal direction

– I = Input

– O = Output

– I/O = Input and Output

– D = Open drain

– DS = Differential

– A = Analog

– PWR = Power

– GND = Ground

Note: In the safe_mode, the buffer is configured in high-impedance.

6. BALL RESET STATE: State of the terminal while the active low PWRONRSTn terminal is low.

– 0: The buffer drives V

(pulldown or pullup resistor not activated)

0(PD): The buffer drives V

with an active pulldown resistor

– 1: The buffer drives V

(pulldown or pullup resistor not activated)

1(PU): The buffer drives V

with an active pullup resistor

– Z: High-impedance

– L: High-impedance with an active pulldown resistor

– H : High-impedance with an active pullup resistor

7. BALL RESET REL. STATE: State of the terminal after the active low PWRONRSTn terminal

transitions from low to high.

– 0: The buffer drives V

(pulldown or pullup resistor not activated)

0(PD): The buffer drives V

with an active pulldown resistor

– 1: The buffer drives V

(pulldown or pullup resistor not activated)

1(PU): The buffer drives V

with an active pullup resistor

– Z: High-impedance.

– L: High-impedance with an active pulldown resistor

– H : High-impedance with an active pullup resistor

8. RESET REL. MODE: The mode is automatically configured after the active low PWRONRSTn terminal

transitions from low to high.

9. POWER: The voltage supply that powers the I/O buffers of the terminal.

Submit Documentation Feedback

Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351

ZHCS488J –OCTOBER 2011–REVISED APRIL 2016

www.ti.com.cn

Table 4-2. Pin Attributes (ZCE and ZCZ Packages)

ZCE BALL

NUMBER [1]

ZCZ BALL

NUMBER [1]

PIN NAME [2] SIGNAL NAME [3] MODE [4]

TYPE

[5]

BALL RESET

STATE [6]

(25)

BALL RESET

REL. STATE

[7]

RESET REL.

MODE [8]

ZCE POWER /

ZCZ POWER [9]

HYS

[10]

BUFFER

STRENGTH

(mA) [11]

PULLUP

/DOWN TYPE

[12]

I/O CELL [13]

B8 B6 AIN0 AIN0 0 A

(22)

Z Z 0 VDDA_ADC /

VDDA_ADC

NA 25 NA Analog

A11 C7 AIN1 AIN1 0 A

(21)

Z Z 0 VDDA_ADC /

VDDA_ADC

NA 25 NA Analog

A8 B7 AIN2 AIN2 0 A

(21)

Z Z 0 VDDA_ADC /

VDDA_ADC

NA 25 NA Analog

B11 A7 AIN3 AIN3 0 A

(20)

Z Z 0 VDDA_ADC /

VDDA_ADC

NA 25 NA Analog

C8 C8 AIN4 AIN4 0 A

(20)

Z Z 0 VDDA_ADC /

VDDA_ADC

NA 25 NA Analog

B12 B8 AIN5 AIN5 0 A Z Z 0 VDDA_ADC /

VDDA_ADC

NA NA NA Analog

A10 A8 AIN6 AIN6 0 A Z Z 0 VDDA_ADC /

VDDA_ADC

NA NA NA Analog

A12 C9 AIN7 AIN7 0 A Z Z 0 VDDA_ADC /

VDDA_ADC

NA NA NA Analog

C13 C10 CAP_VBB_MPU CAP_VBB_MPU NA A

D6 D6 CAP_VDD_RTC CAP_VDD_RTC NA A

B10 D9 CAP_VDD_SRAM_CORE CAP_VDD_SRAM_CORE NA A

D13 D11 CAP_VDD_SRAM_MPU CAP_VDD_SRAM_MPU NA A

F3 F3 DDR_A0 ddr_a0 0 O H 1 0 VDDS_DDR /

VDDS_DDR

NA 8 PU/PD LVCMOS/SSTL/

HSTL

J2 H1 DDR_A1 ddr_a1 0 O H 1 0 VDDS_DDR /

VDDS_DDR

NA 8 PU/PD LVCMOS/SSTL/

HSTL

D1 E4 DDR_A2 ddr_a2 0 O H 1 0 VDDS_DDR /

VDDS_DDR

NA 8 PU/PD LVCMOS/SSTL/

HSTL

B3 C3 DDR_A3 ddr_a3 0 O H 1 0 VDDS_DDR /

VDDS_DDR

NA 8 PU/PD LVCMOS/SSTL/

HSTL

E5 C2 DDR_A4 ddr_a4 0 O H 1 0 VDDS_DDR /

VDDS_DDR

NA 8 PU/PD LVCMOS/SSTL/

HSTL

A2 B1 DDR_A5 ddr_a5 0 O H 1 0 VDDS_DDR /

VDDS_DDR

NA 8 PU/PD LVCMOS/SSTL/

HSTL

B1 D5 DDR_A6 ddr_a6 0 O H 1 0 VDDS_DDR /

VDDS_DDR

NA 8 PU/PD LVCMOS/SSTL/

HSTL

D2 E2 DDR_A7 ddr_a7 0 O H 1 0 VDDS_DDR /

VDDS_DDR

NA 8 PU/PD LVCMOS/SSTL/

HSTL

C3 D4 DDR_A8 ddr_a8 0 O H 1 0 VDDS_DDR /

VDDS_DDR

NA 8 PU/PD LVCMOS/SSTL/

HSTL

B2 C1 DDR_A9 ddr_a9 0 O H 1 0 VDDS_DDR /

VDDS_DDR

NA 8 PU/PD LVCMOS/SSTL/

HSTL

E2 F4 DDR_A10 ddr_a10 0 O H 1 0 VDDS_DDR /

VDDS_DDR

NA 8 PU/PD LVCMOS/SSTL/

HSTL

G4 F2 DDR_A11 ddr_a11 0 O H 1 0 VDDS_DDR /

VDDS_DDR

NA 8 PU/PD LVCMOS/SSTL/

HSTL

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