EFM8BB52微控制器参考手册：小体积，大功能

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EFM8BB52是一款属于8位微控制器（MCU）系列的Busy Bee Family产品，其目标市场是空间受限的应用。这款小巧的单片机集成了多种高级模拟和通信外围设备，提供了卓越的价值，特别适合于嵌入式系统设计。它基于高效的8051内核，最高可工作在50MHz频率，具有出色的功耗效率。核心特性包括： 1. **8051内核**：采用了流水线设计，提升了指令处理速度，能够满足高性能应用的需求。 2. **多功能I/O端口**：最多支持29个5伏特供电的多功能输入输出引脚，使得外部接口灵活且多样化。 3. **模拟与数字转换器**：集成1个12位的ADC（模拟到数字转换器）和1个10位DAC（数字到模拟转换器），支持精确的数据转换。 4. **模拟比较器**：内置两个模拟比较器，可用于检测电压或电流的阈值，广泛应用于信号检测。 5. **温度传感器**：集成用于监测环境温度的传感器，方便实时监控系统性能。 6. **PWM与定时器**：包含3通道PWM（脉宽调制）引擎和3通道带下降沿触发输入的PWM，支持高精度定时和脉冲控制。 7. **多路定时器**：4个16位和2个8位定时器，满足不同精度和周期性的计时需求。 8. **串行通信接口**：内置2个UART（通用异步收发器）和2个SMBus/I2C接口，便于设备间的数据通信。 9. **SPI接口**：带有4字节的FIFO（先进先出队列），提供高效的数据传输机制。 10. **交叉bar总线**：优先级设计的总线架构，允许用户灵活配置引脚功能。 11. **可编程逻辑单元**：4个可配置的逻辑单元，为用户提供自定义逻辑设计的灵活性。 12. **应用领域广泛**：支持LED照明控制、工业自动化和消费电子等多个行业，具有高度的通用性和适应性。 EFM8BB52以其全面的功能、高效能和小型化设计，成为了众多空间受限项目中理想的解决方案，尤其适合对性能、功耗和接口灵活性有较高要求的应用场景。

1.3 Memory

The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory

spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different

instruction types. Program memory consists of a non-volatile storage area that may be used for either program code or non-volatile

data storage. The data memory, consisting of "internal" and "external" data space, is implemented as RAM, and may be used only for

data storage. Program execution is not supported from the data memory space.

Program Memory

The CIP-51 core has a 64 KB program memory space. The product family implements some of this program memory space as in-sys-

tem, re-programmable flash memory. Flash security is implemented by a user-programmable location in the flash block and provides

read, write, and erase protection. All addresses not specified in the device memory map are reserved and may not be used for code or

data storage.

Data Memory

The RAM space on the chip includes both an "internal" RAM area which is accessed with MOV instructions, and an on-chip "external"

RAM area which is accessed using MOVX instructions. Total RAM varies, based on the specific device. The device memory map has

more details about the specific amount of RAM available in each area for the different device variants.

EFM8BB52 Reference Manual

System Overview

silabs.com | Building a more connected world. Rev. 0.3 | 16

1.5 I/O

Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P2.7 can be defined as gen-

eral-purpose I/O (GPIO) or assigned to one of the internal digital resources through the crossbar or dedicated channels. Port pins P0.0-

P3.1 can be assigned to an analog function. Port pins P3.0 to P3.7 can be used as GPIO. Additionally, the C2 Interface Data signal

(C2D) is shared with P2.0 or P3.7, depending on the package option. Not all pins are present in all devices and this is dependent on the

chosen device package(s). The pinout differences are covered in the device datasheet.

The port control block offers the following features:

• Up to 29 multi-function I/O pins, supporting digital and analog functions.

• Flexible priority crossbar decoder for digital peripheral assignment.

• Two drive strength settings for each port.

• State retention feature allows pins to retain configuration through most reset sources.

• Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1).

• Up to 24 direct-pin interrupt sources with shared interrupt vector (Port Match).

1.6 Clocking

The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources. By default, the system

clock comes up running from the HFOSC 24.5 MHz output divided by 8 (3.0625 MHz).

The clock control system offers the following features:

• Provides clock to core and peripherals.

• Configurable system clock source:

• 49 MHz internal oscillator (HFOSC), accurate to ±2% across process, supply, and temperature corners

• 10 MHz internal oscillator (FSOSC), fast-startup, low power

• 80 kHz low-frequency oscillator (LFOSC)

• CMOS external clock input (EXTCLK)

• 24.5 MHz clock from HFOSC

• 24.5 MHz clock from HFOSC divided by 1.5 (16.33 MHz)

• 2.5 MHz clock from FSOSC

• 49 MHz clock from HFOSC divided by 1.5 (32.67 MHz)

• Clock divider with eight settings for flexible clock scaling:

• Divide the selected clock source by 1, 2, 4, 8, 16, 32, 64, or 128

1.7 Counters/Timers and PWM

Programmable Counter Array (PCA0)

The programmable counter array (PCA) provides multiple channels of enhanced timer and PWM functionality while requiring less CPU

intervention than standard counter/timers. The PCA consists of a dedicated 16-bit counter/timer and one 16-bit capture/compare mod-

ule for each channel. The counter/timer is driven by a programmable timebase that has flexible external and internal clocking options.

Each capture/compare module may be configured to operate independently in one of five modes: Edge-Triggered Capture, Software

Timer, High-Speed Output, Frequency Output, or Pulse-Width Modulated (PWM) Output. Each capture/compare module has its own

associated I/O line (CEXn) which is routed through the crossbar to port I/O when enabled.

• 16-bit time base

• Programmable clock divisor and clock source selection

• Up to three independently-configurable channels

• 8, 9, 10, 11 and 16-bit PWM modes (center or edge-aligned operation)

• Output polarity control

• Frequency output mode

• Capture on rising, falling or any edge

• Compare function for arbitrary waveform generation

• Software timer (internal compare) mode

• Can accept hardware “kill” signal from comparator 0 or comparator 1

EFM8BB52 Reference Manual

System Overview

silabs.com | Building a more connected world. Rev. 0.3 | 20

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