AMD Family 10h 处理器 BIOS 和内核开发者指南

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"BIOS and Kernel Developer’s Guide for AMD Processor" AMD 家族10h处理器的BIOS和内核开发者指南（BKDG）是一份技术文档，旨在为那些致力于在AMD平台上进行BIOS和内核开发的专业人员提供详尽的指导。这份31116Rev3.00版的指南发布于2007年9月7日，涵盖了与AMD Family 10h系列处理器相关的硬件接口、系统初始化过程以及内核开发的关键信息。 AMD Family 10h处理器是AMD公司推出的一代高性能处理器，可能包括Phenom、Athlon等系列产品。BIOS（基本输入输出系统）是计算机启动时运行的第一段软件，负责硬件初始化和引导操作系统。而内核则是操作系统的核心，管理硬件资源并提供基础服务。这份指南对于理解AMD处理器的工作原理，优化系统性能，以及解决兼容性和稳定性问题至关重要。指南中可能会涵盖以下关键知识点： 1. **处理器架构**：AMD Family 10h处理器的微架构，包括核心数量、缓存层次结构、内存控制器和超传输（HyperTransport）总线技术。 2. **系统初始化流程**：POST（Power-On Self Test）过程，CMOS设置，BIOS固件更新机制，以及如何在不同阶段与处理器交互。 3. **硬件接口**：如PCIe、SATA、USB等接口的配置和管理，以及如何通过BIOS进行设置。 4. **处理器特性**：如AMD的3DNow!、MMX指令集，多线程技术，以及能源管理特性。 5. **内核开发**：针对AMD处理器优化的Linux或Windows内核配置，中断处理，设备驱动编写，以及性能调优。 6. **调试工具和方法**：如何使用调试器和其他工具来诊断和修复BIOS或内核级问题。 7. **电源管理**：AMD处理器支持的ACPI（高级配置和电源接口）规范，以及C状态（C States）和P状态（P States）的实现。 8. **安全特性**：如Secure Boot、TPM（可信平台模块）集成，以及如何在BIOS级别实现这些功能。 9. **兼容性**：与不同类型的内存（DDR2/DDR3）、显卡和其他外设的兼容性测试和配置。 10. **变更历史**：文档的修订版本记录，以便开发者了解最新的技术和修正。 AMD的这份开发者指南是技术工程师和系统构建者的重要参考资料，帮助他们在设计、调试和优化基于AMD Family 10h处理器的系统时，能够充分利用硬件潜能，提高系统的可靠性和效率。由于AMD处理器广泛应用于服务器、工作站和个人电脑，这份文档对于整个IT行业的专业人员都有着重要的价值。

31116 Rev 3.00 - September 07, 2007 AMD Family 10h Processor BKDG

•LINT. Local interrupt.

• Logical DIMM. Either one 64-bit DIMM or two identical DIMMs in parallel to create a 128-bit interface.

See section 2.8 [DRAM Controllers (DCTs)] on page 60.

• LVT. Local vector table. A collection of APIC registers that define interrupts for local events. E.g., [The

Extended Interrupt [3:0] Local Vector Table Registers] APIC[530:500].

• Master abort. This is a PCI-defined term that is applied to transactions on other than PCI busses. It indicates

that the transaction is terminated without affecting the intended target; reads return all 1’s; writes are dis-

carded; the master abort error code is returned in the response, if applicable; master abort error bits are set if

applicable.

• MB or Mbyte. Megabyte; 1024 Kbytes.

• MCT. Memory controller. See section 2.6.1 [Northbridge (NB) Architecture] on page 50.

• MCQ. Memory controller queue. See section 2.6.1 [Northbridge (NB) Architecture] on page 50.

• MEMCLK. Refers to the clock signals, M[B, A][3:0]_CLK, that are driven from the processor to DDR

DIMMs.

• MMIO. Memory-mapped input-output range. This is physical address space that is mapped to the IO func-

tions such as the IO links or MMIO configuration. The IO link MMIO ranges are specified by [The Memory

Mapped IO Base/Limit Registers] F1x[BC:80].

• MMIO configuration. Access to configuration space through memory space. See section 2.11 [Configura-

tion Space] on page 112.

• MOF. Maximum operating frequency of the CPU core(s). Normally this is the CPU core COF in P-state 0.

See section 2.4.2 [P-states] on page 31.

• MSR. Model specific register. The CPU includes several MSRs for general configuration and control. See

section 3.10 [MSRs - MSR0000_xxxx] on page 291 for the beginning of the MSR register definitions.

• MTRR. Memory-type range register. The MTRRs specify the type of memory associated with various mem-

ory ranges. See MSR0000_00FE, MSR0000_02[0F:00], MSR0000_02[6F:68, 59, 58, 50], and

MSR0000_02FF.

• NB. Northbridge. The transaction routing block of the node. See section 2.1 [Processor Overview] on page

21.

•

NCLK. The main Northbridge clock. The NCLK frequency is the NB COF.

• Node ID. The identifier assigned to each node, [The Node ID Register] F0x60[NodeId].

• Node. See section 2.1 [Processor Overview] on page 21.

• Normalized address. Addresses used by DCTs. See section 2.6.1 [Northbridge (NB) Architecture] on page

50.

• Octword. A 128-bit value.

• ODM. On-DIMM mirroring. See F2x[1, 0][5C:40][OnDimmMirror].

• ODT. On-die termination, which is applied DRAM interface signals.

• ODTS. DRAM On-die thermal sensor.

• Operational frequency. The frequency at which the processor operates. See section 2.4 [Power Manage-

ment] on page 25.

• PDS. Product data sheet. See section 1.2 [Reference Documents] on page 12.

•PRBS. Pseudo-random bit sequence.

• Processor. See section 2.1 [Processor Overview] on page 21.

• P-state. Performance state. See section 2.4 [Power Management] on page 25.

• PTE. Page table entry.

31116 Rev 3.00 - September 07, 2007 AMD Family 10h Processor BKDG

• PVI. Parallel VID interface. See section 2.4.1 [Processor Power Planes And Voltage Control] on page 25.

• Quadword. A 64-bit value.

• RAS. Reliability, availability and serviceability (industry term). See section 2.13 [RAS and Advanced Server

Features] on page 113.

• RX. Receiver.

• SBI. Sideband Interface. Also referred to as APML. See section 2.13.3 [Sideband Interface (SBI)] on page

121.

• Scrubber. Background memory checking logic. See section 2.6.6 [Memory Scrubbers] on page 54.

•Shutdown. A state in which the affected core waits for either INIT, RESET, or NMI. When shutdown state is

entered, a shutdown special cycle is sent on the IO links.

•Single-Plane. Refers to a processor or systemboard where VDD and VDDNB are tied together and operate

at the same voltage level. Refer to 2.4.1 [Processor Power Planes And Voltage Control] on page 25.

• Slam. Refers to change the voltage to a new value in one step (as opposed to stepping). See section 2.4.1.8

[Hardware-Initiated Voltage Transitions] on page 30.

• SMAF. System management action field. This is the code passed from the SMC to the processors in STP-

CLK assertion messages. The action taken by the processors in response to this message is specified by [The

ACPI Power State Control Registers] F3x[84:80].

•SMBus. System management bus. Refers to the protocol on which the serial VID interface (SVI) commands

and SBI are based. See section 2.4.1 [Processor Power Planes And Voltage Control] on page 25, 2.13.3

[Sideband Interface (SBI)] on page 121, and section 1.2 [Reference Documents] on page 12.

• SMC. System management controller. This is the platform device that communicates system management

state information to the processor through an IO link, typically the system IO Hub.

• SMI. System management interrupt. See section 2.14.2.1 [SMM Overview] on page 124.

• SMM. System management mode. See section 2.14.2 [System Management Mode (SMM)] on page 124.

• Southbridge. Same as IO Hub.

• Speculative event. A performance monitor event counter that counts all occurrences of the event even if the

event occurs during speculative code execution.

•STC. Software thermal control. See section 2.10.3.2 [Software Thermal Control (STC)] on page 111

• STC-active state. Software-controlled lower-power, lower-performance state used to reduce temperature.

See section 2.10.3.2 [Software Thermal Control (STC)] on page 111.

• STC thermal zone. Temperature range which may be programmed to generate interrupts and special bus

cycles. See section 2.10.3.2 [Software Thermal Control (STC)] on page 111.

• Sublink. An 8-bit-or-less (CAD) block of link signals of a link; each sublink of a link may connect to a dif-

ferent device. See section 2.7 [Links] on page 55.

• SVI. Serial VID interface. See section 2.4.1 [Processor Power Planes And Voltage Control] on page 25.

• SVM. secure virtual machine. See section 2.15 [Secure Virtual Machine Mode (SVM)] on page 132.

• Sync flood. The propagation of continuous sync packets to all links. See the link specification.

• TCB. Trace capture buffer.

• TCC. Temperature calculation circuit. See section 2.10 [Thermal Functions] on page 110.

• Tctl. Processor temperature control value. See section 2.10.3 [Temperature-Driven Logic] on page 110.

• Thermal diode. A diode connected to the THERMDA and THERMDC pins used for thermal measure-

ments. See section 2.10.2 [Thermal Diode] on page 110.

•Token. A scheduler entry used in various Northbridge queues to track outstanding requests. See [The SRI to

XCS Token Count Register] F3x140 on Page 461.

31116 Rev 3.00 - September 07, 2007 AMD Family 10h Processor BKDG

• TX. Transmitter.

• UI. Unit interval. This is the amount of time equal to one half of a clock cycle.

• Unganged. A link, memory channel, or voltage regulator in which portions are controlled separately.

•US. Upstream. Refers to the direction of data on a link.

• usec. Microsecond.

• VDD. Main power supply to the processor core logic.

• VDDNB. Main power supply to the processor NB logic.

• VID. Voltage level identifier. See section 2.4.1 [Processor Power Planes And Voltage Control] on page 25.

• Virtual CAS. The clock in which CAS is asserted for the burst, N, plus the burst length (in MEMCLKs),

minus 1; so the last clock of virtual CAS = N + BL/2 - 1.

• VRM. voltage regulator module.

• Warm reset. RESET_L is asserted only (while PWROK stays high). See section 2.3 [Processor Initializa-

tion] on page 22.

• WDT. Watchdog timer. A timer that detects activity and triggers an error if a specified period of time expires

without the activity. For example, see [The CPU Watchdog Timer Register (CpuWdTmrCfg)]

MSRC001_0074.

• XBAR. Cross bar; command packet switch. See section 2.6.1 [Northbridge (NB) Architecture] on page 50.

1.5 Changes Between Revisions and Product Variations

1.5.1 Major Changes For Revision A Relative to Family 0Fh Processors

• CPU core additions:

• Support for up to 4 CPU cores in product variations.

• High-performance (128-bit internal data path) floating point unit (per CPU core) in product variations.

• SSE4A instructions.

• Advanced bit manipulation (ABM) instructions.

• MWAIT and MONITOR instructions.

• Misaligned SSE mode.

• Power management state invariant time stamp counter (TSC).

• Number of extended LVT interrupts in APIC increased to 4.

• Increase in the number of large TLB page entries.

• 1 Gbyte large paging supported.

• Physical address space increased to 48 bits.

• All local sources of SMIs (including sources from the CPU cores and from the NB) are broadcast to all

CPU cores of all nodes in the system.

• Memory controller (MCT) and DRAM controllers (DCTs) additions:

• Support for DDR2/DDR3 DIMMs in product variations.

• DIMMs controlled through two independent DRAM controllers.

• Write burst and DRAM prefetching performance improvements.

• Read and write burst support, as required for DRAM training.

• Links and IO additions:

• HyperTransport™ 3.00 Technology, including support for DC- and AC-coupled modes.

• Link unganging support.

• Link-defined extended address capability to support up to 64-bit IO addresses.

• Link-defined UnitID clumping.

• Link-defined error retry.

• Link-defined isochronous flow control mode.

31116 Rev 3.00 - September 07, 2007 AMD Family 10h Processor BKDG

• Link-defined INTx support.

• Support for independent ordering between requests with different non-zero SeqID values.

• Asynchronous link support (with different oscillator sources generating the reference clock on both sides

of the link).

• RAS-related additions:

• CPU core disable capability.

• New error thresholding support for errors associated with links, and the L3 cache; all the thresholding

registers are additionally accessible through configuration space.

• New configurable responses to link errors: data error to target abort; master abort to no error; configura-

tion space master abort to no error; sync flood on data errors; sync flood on target aborts.

• Added another MCA bank for a CPU watchdog timer.

• MCA control mask registers control logging in addition to reporting of errors.

• Link protocol checking.

• Ability to convert machine check exceptions into vectored interrupts or SMIs.

• General Northbridge additions:

• Support for an L3 cache, shared between CPU cores, in product variations.

• BIOS-initiated system memory clear command.

• MMIO-based access to configuration space and support for extended configuration space; this includes

support for SMI traps to these accesses as well.

• SMBus-based access to internal processor state called sideband interface (SBI) also referred to as

APML.

• Mode whereby the IO request response order matches the IO request order.

• VGA space decoding to MMIO-space mapping registers.

• Support for multiple, simultaneous GART/DEV table walks.

• Support for evenly distributed traffic in systems that connect multiple links between the same processors.

• More DEV protection domains and a larger DEV cache.

• Ability to force all IO requests to system memory (except display refresh) to probe the cache, in support

of nested paging.

• Combined link status register for all links.

• Power management:

• Simple “fire and forget” operating system interface for P-state changes.

• Separate CPU core and Northbridge power and clock planes.

• Support for up to 5 independent P-states for each CPU core.

• Support for P-state limits controlled by sideband interface (SBI), thermal limits (HTC), or host software;

used to limit the P-state requested by the operating system in order to reduce power.

• Support for Northbridge and CPU core alternate voltages (altvid) during C3.

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