Contents
ï 1.0 Introduction
ï 2.0 ST-BUS Form and Signals
ï 3.0 Clocking Signals
ï 4.0 Alignment Signals
ï 5.0 Information Streams
ï 6.0 Worst Case Timing Parameters
ï 7.0 Nomenclature
7.1 Clock Signals
7.2 Framing Signals
7.3 ST-BUS streams
1.0 Introduction
As systems become more complex, the trend in
system design has been to partition circuitry into well
defined functional blocks. Such partitioning localizes
circuitry performing a particular function to a specific
location in a system, thus promoting modularity.
Modularity is an important consideration, particularly
for flexibility in system configuration. Modularity is
also a good defence against obsolescence. The
amount of investment in a system design makes it
expensive to throw away, especially when only
portions may be outdated. This is avoided by
improving the outdated portions and keeping the rest
of the system. These design philosophies can only
be implemented if the system is designed modularly
from the beginning.
It is necessary to have a well defined, effective
means of communication and information transfer
between modules (the term information is used here
because it can apply equally to audio, video, control
information or data). The definition of a common
interface between functional blocks eases the
addition of new circuitry to a design. Such an
interface should be simple, to allow modules to have
a wide range of complexity. The interface should be
capable of being overlayed by higher levels of
communication protocol such as High Level Data
Link Control (HDLC), for instances where
communication needs are more demanding. There is
no need to constrain module design where such a
protocol is not needed.
Zarlink Semiconductor has defined the ST-BUS (Serial
Telecom Bus) with the above requirements in mind.
It is simple to interface to, and can handle all four
types of information mentioned, when the
information is digitized. The ST-BUS Generic Device
Specification presented in Tables 1 and 2 of this
document encompasses the ìworst caseî timing
parameters of the ST-BUS interface for different data
rates. New ST-BUS compatible components or
circuits must conform to these minimum and
maximum timing specifications, or be better, to
ensure compatibility with all components and
systems that already exist. A system designer may
use these overall component timing specifications to
aid in the interconnection of ST-BUS devices.
2.0 ST-BUS Form and Signals
The ST-BUS is a high speed, synchronous serial bus
for transporting information in a digital format. The
use of serial streams minimizes the printed circuit
board area needed for information transfer between
functional modules. Fewer tracks, backplane
connections, and intra-shelf cables are needed
compared to systems that use parallel paths. These
considerations become critical in systems that have
a high information flow density, with many
simultaneous communications occurring between
functional modules. At the integrated circuit level, the
benefits of using a serial interface on an IC are
reduced pin count, improved reliability and
decreased power dissipation.
The signals required to interface to the ST-BUS are:
i) A framing signal for frame alignment
ii) A clock signal for bit timing
iii) Serial information streams
Depending on the application, the aggregate rate of
the ST-BUS information stream can be 2.048, 4.096
or 8.192 Mbit/s. This stream is divided into frames,
each frame having a period of 125 µs, for a frame
rate of 8000 frames/s. The start of each ST-BUS
frame is indicated by the framing signal (frame
pulse). Each frame is divided into an integer number
of bit periods, with bit timing provided by the clock
signal (see Figure 1). This information stream could
be considered a single high speed communication
channel between two points, however, the full digital
bandwidth is not needed for many applications. It is
therefore useful to divide this high speed channel
into multiple, lower bandwidth channels. This makes
it possible to share the capacity of one serial
ST-BUS stream among several channels, referenced
ISSUE 4 June 1995
MSAN-126
ST-BUS Generic Device Specification
(Rev. B)
Application Note