ST-BUS标准详解：模块化系统通信的关键

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"ST-BUS标准是系统设计中的一个重要通信接口规范，它允许系统中的不同功能模块之间进行高效、可靠的通信。随着系统复杂性的增加，将电路分割成具有明确功能的块成为了设计趋势，以实现系统的模块化。模块化设计不仅提高了系统配置的灵活性，还能对抗过时，因为可以通过更新部分模块而不是整体替换来保持系统的先进性。 ST-BUS标准详细定义了通信总线的形式和信号，包括以下几个关键方面： 1.0 Introduction: 引言部分阐述了ST-BUS标准的重要性和背景，强调了模块化设计在复杂系统中的必要性，以及通信接口在模块间信息传递中的作用。 2.0 ST-BUS Form and Signals: 这一部分详细介绍了ST-BUS的物理结构和信号特性，包括总线的引脚布局、电气特性以及信号的时序。 3.0 Clocking Signals: 时钟信号是ST-BUS中至关重要的部分，它们定义了数据传输的同步节奏。这部分可能涵盖了时钟信号的频率、相位和稳定性要求。 4.0 Alignment Signals: 对齐信号确保数据在正确的时间被接收和处理，防止数据错位。这部分可能会涉及帧同步信号和其他辅助同步机制。 5.0 Information Streams: 信息流部分描述了如何通过ST-BUS传输数据，可能包括数据包格式、错误检测和纠正机制，以及流量控制策略。 6.0 Worst Case Timing Parameters: 最差情况下的定时参数分析了ST-BUS在最不利条件下的性能边界，这有助于系统设计者确保在各种环境条件下ST-BUS的可靠性。 7.0 Nomenclature: 名词解释部分提供了ST-BUS相关术语的定义，便于理解和应用标准。具体包括时钟信号、帧信号和ST-BUS流的术语。 7.1 Clock Signals: 对时钟信号的详细定义，包括时钟信号的不同类型、用途和相关的时序参数。 7.2 Framing Signals: 帧信号部分详细介绍了用于标识数据包开始和结束的信号，以及它们如何帮助接收端正确解析信息流。 7.3 ST-BUS streams: 这里进一步阐述了ST-BUS的数据流概念，可能包括流的分配、多路复用和解复用机制，以及如何处理不同优先级的数据流。 ST-BUS标准的实施使得不同模块之间的交互变得标准化，降低了设计复杂性，增强了系统的可扩展性和维护性。理解并遵循这个标准对于构建高效、可靠且易于升级的模块化系统至关重要。"

Contents

ï 1.0 Introduction

ï 2.0 ST-BUS Form and Signals

ï 3.0 Clocking Signals

ï 4.0 Alignment Signals

ï 5.0 Information Streams

ï 6.0 Worst Case Timing Parameters

ï 7.0 Nomenclature

7.1 Clock Signals

7.2 Framing Signals

7.3 ST-BUS streams

1.0 Introduction

As systems become more complex, the trend in

system design has been to partition circuitry into well

defined functional blocks. Such partitioning localizes

circuitry performing a particular function to a specific

location in a system, thus promoting modularity.

Modularity is an important consideration, particularly

for flexibility in system configuration. Modularity is

also a good defence against obsolescence. The

amount of investment in a system design makes it

expensive to throw away, especially when only

portions may be outdated. This is avoided by

improving the outdated portions and keeping the rest

of the system. These design philosophies can only

be implemented if the system is designed modularly

from the beginning.

It is necessary to have a well defined, effective

means of communication and information transfer

between modules (the term information is used here

because it can apply equally to audio, video, control

information or data). The definition of a common

interface between functional blocks eases the

addition of new circuitry to a design. Such an

interface should be simple, to allow modules to have

a wide range of complexity. The interface should be

capable of being overlayed by higher levels of

communication protocol such as High Level Data

Link Control (HDLC), for instances where

communication needs are more demanding. There is

no need to constrain module design where such a

protocol is not needed.

Zarlink Semiconductor has defined the ST-BUS (Serial

Telecom Bus) with the above requirements in mind.

It is simple to interface to, and can handle all four

types of information mentioned, when the

information is digitized. The ST-BUS Generic Device

Specification presented in Tables 1 and 2 of this

document encompasses the ìworst caseî timing

parameters of the ST-BUS interface for different data

rates. New ST-BUS compatible components or

circuits must conform to these minimum and

maximum timing specifications, or be better, to

ensure compatibility with all components and

systems that already exist. A system designer may

use these overall component timing specifications to

aid in the interconnection of ST-BUS devices.

2.0 ST-BUS Form and Signals

The ST-BUS is a high speed, synchronous serial bus

for transporting information in a digital format. The

use of serial streams minimizes the printed circuit

board area needed for information transfer between

functional modules. Fewer tracks, backplane

connections, and intra-shelf cables are needed

compared to systems that use parallel paths. These

considerations become critical in systems that have

a high information flow density, with many

simultaneous communications occurring between

functional modules. At the integrated circuit level, the

benefits of using a serial interface on an IC are

reduced pin count, improved reliability and

decreased power dissipation.

The signals required to interface to the ST-BUS are:

i) A framing signal for frame alignment

ii) A clock signal for bit timing

iii) Serial information streams

Depending on the application, the aggregate rate of

the ST-BUS information stream can be 2.048, 4.096

or 8.192 Mbit/s. This stream is divided into frames,

each frame having a period of 125 µs, for a frame

rate of 8000 frames/s. The start of each ST-BUS

frame is indicated by the framing signal (frame

pulse). Each frame is divided into an integer number

of bit periods, with bit timing provided by the clock

signal (see Figure 1). This information stream could

be considered a single high speed communication

channel between two points, however, the full digital

bandwidth is not needed for many applications. It is

therefore useful to divide this high speed channel

into multiple, lower bandwidth channels. This makes

it possible to share the capacity of one serial

ST-BUS stream among several channels, referenced

ISSUE 4 June 1995

MSAN-126

ST-BUS Generic Device Specification

(Rev. B)

Application Note

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