"DS92LV1212A: 16-40 MHz LVDS解串器及时钟恢复模块"

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The TI-DS92LV1212A.pdf document provides information on the DS92LV1212A, a high-performance LVDS (Low Voltage Differential Signaling) deserializer designed for use with the DS92LV1021 Bus LVDS Serializer. The DS92LV1212A is an upgraded version of the DS92LV1212, maintaining all its features while also offering enhanced performance. This deserializer is capable of receiving a Bus LVDS serial data stream and converting it into a 10-bit parallel data output. It operates at frequencies ranging from 16 to 40 MHz, making it suitable for a wide range of applications. Additionally, the DS92LV1212A features embedded clock recovery, allowing for accurate synchronization of data signals. With its high-speed operation and reliable performance, the DS92LV1212A is ideal for use in various communication systems, industrial equipment, and other applications requiring precise data transmission. Its compact design, low power consumption, and compatibility with the DS92LV1021 make it a versatile and cost-effective solution for LVDS serialization and deserialization requirements. In conclusion, the DS92LV1212A is a reliable and efficient LVDS deserializer that offers advanced features and compatibility with other LVDS components. Its high-speed operation, embedded clock recovery, and compact design make it a valuable tool for engineers and designers seeking reliable data transmission solutions in their projects.

Resynchronization (Continued)

recommendation is to provide a feedback loop using the

LOCK pin itself to control the sync request of the Serializer

(SYNC1 or SYNC2). Dual SYNC pins are provided for mul-

tiple control in a multi-drop application. Sending sync pat-

terns for resynchronization is desirable when lock times

within a specific time are critical. However, the Deserializer

can lock to random data, which is discussed in the next

section.

Random Lock Initialization and

Resynchronization

The initialization and resynchronization methods described

in their respective sections are the fastest ways to establish

the link between the Serializer and Deserializer. However,

the DS92LV1212A can attain lock to a data stream without

requiring the Serializer to send special SYNC patterns. This

allows the DS92LV1212A to operate in “open-loop” applica-

tions. Equally important is the Deserializer’s ability to support

hot insertion into a running backplane. In the open loop or

hot insertion case, we assume the data stream is essentially

random. Therefore, because lock time varies due to data

stream characteristics, we cannot possibly predict exact lock

time. The primary constraint on “random” lock time is the

initial phase relation between the incoming data and the

REFCLK when the Deserializer powers up. As described in

the next paragraph, the data contained in the data stream

can also affect lock time.

If a specific pattern is repetitive, the Deserializer could enter

“false lock” - falsely recognizing the data pattern as the

clocking bits. We refer to such a pattern as a repetitive

multi-transition, RMT. This occurs when more than one

Low-High transition takes place in a clock cycle over multiple

cycles. This occurs when any bit, except DIN 9, is held at a

low state and the adjacent bit is held high, creating a 0-1

transition. In the worst case, the Deserializer could become

locked to the data pattern rather than the clock. Circuitry

within the DS92LV1212A can detect that the possibility of

“false lock” exists. The circuitry accomplishes this by detect-

ing more than one potential position for clocking bits. Upon

detection, the circuitry will prevent the LOCK output from

becoming active until the potential “false lock” pattern

changes. The false lock detect circuitry expects the data will

eventually change, causing the Deserializer to lose lock to

the data pattern and then continue searching for clock bits in

the serial data stream. Graphical representations of RMT are

shown on the following page. Please note that RMT only

applies to bits DIN0-DIN8.

Powerdown

When no data transfer occurs, you can use the Powerdown

state. The Serializer and Deserializer use the Powerdown

state, a low power sleep mode, to reduce power consump-

tion. The Deserializer enters Powerdown when you drive

PWRDN and REN low. The Serializer enters Powerdown

when you drive PWRDN low. In Powerdown, the PLL stops

and the outputs enterTRI-STATE, which disables load cur-

rent and reduces supply current to the milliampere range. To

exit Powerdown, you must drive the PWRDN pin high.

Before valid data exchanges between the Serializer and

Deserializer, you must reinitialize and resynchronize the de-

vices to each other. Initialization of the Serializer takes 510

TCLK cycles. The Deserializer will initialize and assert LOCK

high until lock to the Bus LVDS clock occurs.

TRI-STATE

The Serializer enters TRI-STATE when the DEN pin is driven

low. This puts both driver output pins (DO+ and DO−) into

TRI-STATE. When you drive DEN high, the Serializer returns

to the previous state, as long as all other control pins remain

static (SYNC1, SYNC2, PWRDN, TCLK_R/F).

When you drive the REN pin low, the Deserializer enters

TRI-STATE. Consequently, the receiver output pins

(ROUT0–ROUT9) and RCLK will enter TRI-STATE. The

LOCK output remains active, reflecting the state of the PLL.

DS92LV1212A

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