DP83910A：以太网Phy收发器技术规格

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"TI-DP83910A.pdf - 以太网Phy收发器" DP83910A是一款由Texas Instruments（TI）生产的以太网PHY收发器，它属于CMOS SNI（Serial Network Interface）系列。这款芯片的主要功能是为IEEE 802.3以太网/Thin-Ethernet类型的局域网络提供曼彻斯特数据编码和解码。它的设计目标是作为一个直接引脚兼容的替代品，对应于之前的双极型DP8391 SNI。 DP83910A在数据传输过程中扮演着关键角色。当需要发送数据时，它将来自网络接口控制器（NIC）的非归零（NRZ）数据转换成曼彻斯特编码，并以差分方式发送到以太网收发器或电缆。曼彻斯特编码是一种自同步的编码方式，能同时传递时钟和数据，适合长距离传输。在接收数据时，DP83910A的相位锁定环（Phase Lock Loop，PLL）会将收发器接收到的10Mbit/s数据解码回NRZ格式，供NIC进一步处理。这种机制确保了数据在传输过程中的准确性和完整性。这款PHY收发器通常与TI的DP8392 Coaxial Transceiver Interface (CTI)和DP8390 Network Interface Controller (NIC)一起使用，构成一个完整的三芯片解决方案，实现符合IEEE 802.3标准的以太网网络。其中，DP8390 NIC负责网络协议的处理和数据包的交换，DP8392 CTI则处理同轴电缆接口的相关事务，而DP83910A则连接这两者，负责物理层的数据编码和解码。 DP83910A的特性包括但不限于： 1. 支持曼彻斯特编码和解码，确保数据在以太网链路上的正确传输。 2. 提供与DP8390 NIC和DP8392 CTI的无缝集成，简化系统设计。 3. 差分输出增强了信号的抗干扰能力，适合长距离通信。 4. 内置的PLL保证了对10Mbit/s数据速率的精确同步和解码。 5. 设计上考虑了兼容性，可以替代原有的DP8391 SNI，方便升级和维护。总体来说，DP83910A是一款适用于以太网环境的高性能PHY收发器，为局域网络提供了稳定且可靠的物理层连接。它在设计时兼顾了效率、兼容性和可靠性，是构建以太网网络不可或缺的组件。

2.0 Block Diagram

TL/F/9365–2

3.0 Functional Description

The DP83910A consists of five main logical blocks:

a) The oscillator generates the 10 MHz transmit clock signal

for system timing.

b) The Manchester encoder accepts NRZ data from the

controller, encodes the data to Manchester, and trans-

mits it differentially to the transceiver, through the differ-

ential transmit driver.

c) The Manchester decoder receives Manchester data from

the transceiver, converts it to NRZ data and clock pulses,

and sends it to the controller.

d) The collision translator indicates to the controller the

presence of a valid 10 MHz collision signal to the PLL.

e) The loopback circuitry, when asserted, routes the data

from the Manchester encoder back to the PLL decoder.

3.1 OSCILLATOR

The oscillator is controlled by a 20 MHz parallel resonant

crystal connected between X1 and X2 or by an external

clock on X1. The 20 MHz output of the oscillator is divided

by 2 to generate the 10 MHz transmit clock for the control-

ler. The oscillator also provides internal clock signals to the

encoding and decoding circuits.

If a crystal is connected to the DP83910A, it is recommend-

ed that the circuit shown in

Figure 1

be used and that the

components used meet the following:

Crystal XT1: AT cut parallel resonant crystal

Series Resistance:

10X

Specified Load Capacitance: 13.5 pF

Accuracy: 0.005% (50 ppm)

C1, C2: Load Capacitor, 27 pF.

The resistor, R1, in

Figure 1

may be required in order to

minimize frequency drift due to changes in the V

supply

voltage. If R1 is required, it’s value must be carefully select-

ed. R1 decreases the loop gain. Thus, if R1 is made too

large, the loop gain will be greatly reduced and the crystal

will not oscillate. If R1 is made too small, normal variations

in the V

may cause the oscillation frequency to drift out of

specification. As the first rule of thumb, the value of R1

TL/F/9365–15

Note 1: The resistor R1 may be required in order to minimize frequency drift

due to changes in the V

. See text description.

FIGURE 1. Crystal Connection to DP83910A

(see text for component values)

should be made equal to five times the motional resistance

of the crystal.

The motional resistance of 20 MHz crystals is usually in the

range of 10X to 30X. This implies that a reasonable value

for R1 should be in the range of 50X –150X.

The decision of whether or not to include R1 should be

based upon measured variations of crystal frequency as

each of the circuit parameters is varied.

According to the IEEE 802.3 standard, the entire oscillator

circuit (crytsal and amplifier) must be accurate to 0.01%.

When using a crystal, the X1 pin is not guaranteed to pro-

vide a TTL compatible logic output, and should not be used

to drive external standard logic. If additional logic needs to

be driven, then an external oscillator should be used, as

described in the following.

3.2 OSCILLATOR MODULE OPERATION

If the designer wishes to use a crystal clock oscillator, one

that provides the following should be employed:

1) TTL or CMOS output with a 0.01% frequency tolerance

2) 40% –60% duty cycle

2 TTL load output drive (I

3.2 mA)

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