ARM系统开发者指南：设计与优化系统软件

需积分: 12 137 浏览量更新于2024-07-26 1 收藏 3.32MB PDF 举报

"ARM System Developer's Guide: Designing and Optimizing System Software" 《ARM System Developer's Guide》是一本专注于ARM体系结构下系统软件设计与优化的专业书籍。该书由Andrew N. Sloss和Dominic Symes等作者撰写，他们拥有深厚的计算机科学背景和丰富的ARM处理器实践经验。 Andrew N. Sloss是一位英国的资深工程师，他在1992年获得赫里福德郡大学的计算机科学学士学位，并被英国计算机学会认证为特许工程师（C.Eng, MBCS）。自1987年以来，他一直参与ARM处理器相关的工作，积累了大量在ARM平台上开发各种应用的经验。Sloss曾为Emerald Publishing设计了基于ARM2和ARM3处理器的首个中文和埃及象形文字编辑系统。目前，他在ARM Inc.担任技术销售工程师，为开发新产品的企业提供咨询和支持，工作地点位于美国加利福尼亚州的洛斯加托斯。 Dominic Symes则在英国剑桥的ARMLtd.担任软件工程师，自1995年起专注于ARM架构的嵌入式软件开发。他在牛津大学获得了数学学士和博士学位，并且早在1989年就开始接触并编程ARM处理器。这本书深入探讨了在ARM体系结构上构建和优化系统软件的关键技术和策略。内容可能涵盖以下几个方面： 1. ARM处理器架构：包括ARM指令集、处理器模式、寄存器组织、中断处理机制以及与其他硬件组件的交互。 2. 系统设计：讨论如何设计高效的内存管理系统、中断服务程序、设备驱动以及多任务环境。 3. 性能优化：介绍代码优化技巧，如循环展开、指令调度、内存访问优化，以及如何利用ARM的特性来提升软件性能。 4. 嵌入式系统开发：涵盖嵌入式系统的固件开发、引导加载程序、操作系统移植和实时性考虑。 5. 工具链使用：解释如何使用编译器、调试器和其他开发工具来有效地开发和调试ARM系统软件。 6. 硬件接口：介绍与ARM处理器兼容的各种外设和接口，以及如何编写驱动程序进行通信。 7. 软件工程实践：强调测试、调试、版本控制和团队协作在系统级开发中的重要性。通过阅读《ARM System Developer's Guide》，读者将能够全面理解ARM平台上的系统软件开发过程，掌握优化技巧，从而更高效地设计和实现高性能、低功耗的嵌入式系统。对于ARM架构的开发者、系统架构师以及嵌入式软件工程师来说，这是一份宝贵的参考资料。

1.1 The RISC design philosophy

1.2 The ARM Design Philosophy

1.2.1 Instruction Set for Embedded Systems

1.3 Embedded System Hardware

1.3.1 ARM Bus Technology

1.3.2 AMBA Bus Protocol

1.3.3 Memory

1.3.4 Peripherals

1.4 Embedded System Software

1.4.1 Initialization (Boot) Code

1.4.2 Operating System

1.4.3 Applications

1.5

Summary

4 Chapter 1 ARM Embedded Systems

1.1 The RISC design philosophy

The ARM core uses a RISC architecture. RISC is a design philosophy aimed at delivering

simple but powerful instructions that execute within a single cycle at a high clock speed.

The RISC philosophy concentrates on reducing the complexity of instructions performed

by the hardware because it is easier to provide greater ﬂexibility and intelligence in software

rather than hardware. As a result, a RISC design places greater demands on the compiler.

In contrast, the traditional complex instruction set computer (CISC) relies more on the

hardware for instruction functionality, and consequently the CISC instructions are more

complicated. Figure 1.1 illustrates these major differences.

The RISC philosophy is implemented with four major design rules:

1. Instructions—RISC processors have a reduced number of instruction classes. These

classes provide simple operations that can each execute in a single cycle. The compiler

or programmer synthesizes complicated operations (for example, a divide operation)

by combining several simple instructions. Each instruction is a ﬁxed length to allow

the pipeline to fetch future instructions before decoding the current instruction. In

contrast, in CISC processors the instructions are often of variable size and take many

cycles to execute.

2. Pipelines—The processing of instructions is broken down into smaller units that can be

executed in parallel by pipelines. Ideally the pipeline advances by one step on each cycle

for maximum throughput. Instructions can be decoded in one pipeline stage. There is

no need for an instruction to be executed by a miniprogram called microcode as on

CISC processors.

3. Registers—RISC machines have a large general-purpose register set. Any register can

contain either data or an address. Registers act as the fast local memory store for all data

CISC RISC

Compiler

Processor Processor

Code

Generation

Greater

Com

lexit

Greater

Complexity

Code

Generation

Figure 1.1 CISC vs. RISC. CISC emphasizes hardware complexity. RISC emphasizes compiler

complexity.

1.2 The ARM Design Philosophy 5

processing operations. In contrast, CISC processors have dedicated registers for speciﬁc

purposes.

4. Load-store architecture—The processor operates on data held in registers. Separate load

and store instructions transfer data between the register bank and external memory.

Memory accesses are costly, so separating memory accesses from data processing pro-

vides an advantage because you can use data items held in the register bank multiple

times without needing multiple memory accesses. In contrast, with a CISC design the

data processing operations can act on memory directly.

These design rules allow a RISC processor to be simpler, and thus the core can operate

at higher clock frequencies. In contrast, traditional CISC processors are more complex

and operate at lower clock frequencies. Over the course of two decades, however, the

distinction between RISC and CISC has blurred as CISC processors have implemented

more RISC concepts.

1.2 The ARM Design Philosophy

There are a number of physical features that have driven the ARM processor design. First,

portable embedded systems require some form of battery power. The ARM processor has

been speciﬁcally designed to be small to reduce power consumption and extend battery

operation—essential for applications such as mobile phones and personal digital assistants

(PDAs).

High code density is another major requirement since embedded systems have lim-

ited memory due to cost and/or physical size restrictions. High code density is useful for

applications that have limited on-board memory, such as mobile phones and mass storage

devices.

In addition, embedded systems are price sensitive and use slow and low-cost memory

devices. For high-volume applications like digital cameras, every cent has to be accounted

for in the design. The ability to use low-cost memory devices produces substantial savings.

Another important requirement is to reduce the area of the die taken up by the embedded

processor. For a single-chip solution, the smaller the area used by the embedded processor,

the more available space for specialized peripherals. This in turn reduces the cost of the

design and manufacturing since fewer discrete chips are required for the end product.

ARM has incorporated hardware debug technology within the processor so that software

engineers can view what is happening while the processor is executing code. With greater

visibility, software engineers can resolve issues faster, which has a direct effect on the time

to market and reduces overall development costs.

The ARM core is not a pure RISC architecture because of the constraints of its primary

application—the embedded system. In some sense, the strength of the ARM core is that

it does not take the RISC concept too far. In today’s systems the key is not raw processor

speed but total effective system performance and power consumption.

6 Chapter 1 ARM Embedded Systems

1.2.1 Instruction Set for Embedded Systems

The ARM instruction set differs from the pure RISC deﬁnition in several ways that make

the ARM instruction set suitable for embedded applications:

■

Variable cycle execution for certain instructions—Not every ARM instruction executes

in a single cycle. For example, load-store-multiple instructions vary in the number

of execution cycles depending upon the number of registers being transferred. The

transfer can occur on sequential memory addresses, which increases performance since

sequential memory accesses are often faster than random accesses. Code density is also

improved since multiple register transfers are common operations at the start and end

of functions.

■

Inline barrel shifter leading to more complex instructions—The inline barrel shifter is

a hardware component that preprocesses one of the input registers before it is used

by an instruction. This expands the capability of many instructions to improve core

performance and code density. We explain this feature in more detail in Chapters 2, 3,

and 4.

■

Thumb 16-bit instruction set—ARM enhanced the processor core by adding a second

16-bit instruction set called Thumb that permits the ARM core to execute either

16- or 32-bit instructions. The 16-bit instructions improve code density by about

30% over 32-bit ﬁxed-length instructions.

■

Conditional execution—An instruction is only executed when a speciﬁc condition has

been satisﬁed. This feature improves performance and code density by reducing branch

instructions.

■

Enhanced instructions—The enhanced digital signal processor (DSP) instructions were

added to the standard ARM instruction set to support fast 16×16-bit multiplier oper-

ations and saturation. These instructions allow a faster-performing ARM processor in

some cases to replace the traditional combinations of a processor plus a DSP.

These additional features have made the ARM processor one of the most commonly

used 32-bit embedded processor cores. Many of the top semiconductor companies around

the world produce products based around the ARM processor.

1.3 Embedded System Hardware

Embedded systems can control many different devices, from small sensors found on

a production line, to the real-time control systems used on a NASA space probe. All

these devices use a combination of software and hardware components. Each component

is chosen for efﬁciency and, if applicable, is designed for future extension and expansion.

剩余702页未读，继续阅读

齐格飞飞

粉丝: 17
资源: 33

ARM系统开发者指南：设计与优化系统软件

ARM System Developer’s Guide Designing and Optimizing System Software

ARM System Developer's Guide 英文原版

ARM System Developer’s Guide

ARM System Developer's Guide.pdf

ARM System Developer's Guide - Designing and Optimizing System Software

ARM System Developer's Guide: Designing and Optimizing System Software

ARM System Developer's Guide/ARM嵌入式系统开发：软件设计与优化

ARM System Developer's Guide: 设计与优化系统软件

ARM.System.Developer's.Guide-Designing.and.Optimizing.System.Software.pdf

ARM.System.Developer 's.Guide.-.Designing.and.Optimizing.System.Software--example code

最新资源