ADSP-TS101S：300MHz嵌入式处理器，全面数据手册

5星 · 超过95%的资源需积分: 10 180 浏览量更新于2024-07-27 收藏 852KB PDF 举报

ADSP-TS101S是一款由Analog Devices公司开发的嵌入式处理器，它在工业界被广泛应用于需要高性能计算和实时处理能力的领域。数据手册是开发者在设计和使用这款处理器时不可或缺的参考资料，它提供了详尽的技术规格和特性概述。首先，ADSP-TS101S的核心特点是其高达300MHz的3.3ns指令周期率，这意味着它具有极高的运算速度，能快速执行复杂的算法和处理大量数据。这使得它特别适合于实时信号处理、多媒体应用以及对速度敏感的控制系统。内置的6MBit内部存储器（On-Chip-SRAM）确保了足够的数据缓存空间，提高了系统响应速度和效率。该处理器提供了两种封装选项，19mm x 19mm（484球栅阵列）或27mm x 27mm（625球栅阵列），以适应不同尺寸和引脚需求的硬件设计。 ADSP-TS101S具有两个独立的计算块，每个计算块内都包含算术逻辑单元（ALU）、乘法器、移位器和寄存器文件，这支持并行处理，增强了其处理性能。双整数ALU功能则支持数据地址寻址和指针操作，对于需要处理大规模数据结构的应用非常实用。集成的I/O功能丰富，包括14通道DMA控制器，用于高效地传输数据；外部端口和四路链接端口，便于与其他设备通信；SDRAM控制器，支持外部内存扩展；以及程序可配置标志位和两个定时器，有助于系统的同步和监控。此外，还有一个IEEE 1149.1兼容的JTAG测试访问端口，使得芯片级调试变得简单可行。为了实现无缝系统集成，ADSP-TS101S还提供了全局仲裁机制，确保了在多个外设和接口之间的数据流协调。这在多任务和并发环境中尤为重要，可以避免资源冲突和提高整体系统稳定性。在版权方面，TigerSHARC和TigerSHARC logo是Analog Devices公司的注册商标，所有提及的专利权也属于该公司。在使用ADSP-TS101S时，尽管提供的信息被认为准确可靠，但用户仍需注意可能存在的专利侵权风险，并确保在合法范围内操作。 ADSP-TS101S以其强大的性能、丰富的I/O接口和高度兼容性，为嵌入式系统设计师提供了强大的工具，但同时也强调了在使用过程中遵循相关的知识产权规定。阅读并理解数据手册是充分利用该处理器的关键步骤，确保项目的成功实施。

ADSP-TS101S

–8– REV. A

The DMA controller also supports two-dimensional transfers.

The DMA controller can access and transfer two-dimensional

memory arrays on any DMA transmit or receive channel. These

transfers are implemented with index, count, and modify

registers for both the X and Y dimensions.

The DMA controller performs the following DMA operations:

• External port block transfers. Four dedicated bidirec-

tional DMA channels transfer blocks of data between the

DSP’s internal memory and any external memory or

memory-mapped peripheral on the external bus. These

transfers support master mode and handshake mode

protocols.

• Link port transfers. Eight dedicated DMA channels (four

transmit and four receive) transfer quad word data only

between link ports and between a link port and internal

or external memory. These transfers only use handshake

mode protocol. DMA priority rotates between the four

receive channels.

• AutoDMA transfers. Two dedicated unidirectional DMA

channels transfer data received from an external bus

master to internal memory or to link port I/O. These

transfers only use slave mode protocol, and an external

bus master must initiate the transfer.

Link Ports

The DSP’s four link ports provide additional 8-bit bidirectional

I/O capability. With the ability to operate at a double data rate—

latching data on both the rising and falling edges of the clock—

running at 125 MHz, each link port can support up to

250M bytes per second, for a combined maximum throughput

of 1G bytes per second.

The link ports provide an optional communications channel that

is useful in multiprocessor systems for implementing point to

point interprocessor communications. Applications can also use

the link ports for booting.

Each link port has its own double-buffered input and output

registers. The DSP’s core can write directly to a link port’s

transmit register and read from a receive register, or the DMA

controller can perform DMA transfers through eight (four

transmit and four receive) dedicated link port DMA channels.

Each link port has three signals that control its operation.

LxCLKOUT and LxCLKIN implement clock/acknowledge

handshaking. LxDIR indicates the direction of transfer and is

used only when buffering the LxDAT signals. An example appli-

cation would be using differential low-swing buffers for long

twisted-pair wires. LxDAT provides the 8-bit data bus

input/output.

Applications can program separate error detection mechanisms

for transmit and receive operations (applications can use the

checksum mechanism to implement consecutive link port trans-

fers), the size of data packets, and the speed at which bytes are

transmitted.

Under certain conditions, the link port receiver can initiate a

token switch to reverse the direction of transfer; the transmitter

becomes the receiver and vice versa.

Timer and General-Purpose I/O

The ADSP-TS101S has a timer pin (TMR0E) that generates

output when a programmed timer counter has expired. Also, the

DSP has four programmable general-purpose I/O pins

(FLAG3–0) that can function as either single bit input or output.

As outputs, these pins can signal peripheral devices; as inputs,

they can provide the test for conditional branching.

Reset and Booting

The ADSP-TS101S has two levels of reset (

see reset specifica-

tions

on Page 22

)

• Power-up reset—After power-up of the system, and strap

options are stable, the RESET pin must be asserted (low).

• Normal reset—For any resets following the power-up

reset sequence, the RESET pin must be asserted.

The DSP can be reset internally (core reset) by setting the

SWRST bit in SQCTL. The core is reset, but not the external

port or I/O.

After reset, the ADSP-TS101S has four boot options for

beginning operation:

• Boot from EPROM. The DSP defaults to EPROM

booting when the BMS pin strap option is set low. See

STRAP PIN FUNCTION DESCRIPTIONS on

Page 18.

• Boot by an external master (host or another ADSP-

TS101S). Any master on the cluster bus can boot the

ADSP-TS101S through writes to its internal memory or

through auto DMA.

• Boot by link port. All four receive link DMA channels are

initialized after reset to transfer a 256-word block to

internal memory address 0 to 255, and to issue an

interrupt at the end of the block (similar to EP DMA).

The corresponding DMA interrupts are set to address

zero (0).

• No boot—Start running from an external memory. Using

the ‘no boot’ option, the ADSP-TS101S must start

running from an external memory, caused by asserting

one of the IRQ3–0 interrupt signals.

The ADSP-TS101S core always exits from reset in the idle state

and waits for an interrupt. Some of the interrupts in the interrupt

vector table are initialized and enabled after reset.

Low Power Operation

The ADSP-TS101S can enter a low power sleep mode in which

its core does not execute instructions, reducing power consump-

tion to a minimum. The ADSP-TS101S exits sleep mode when

it senses a falling edge on any of its

IRQ3–0

interrupt inputs. The

interrupt, if enabled, causes the ADSP-TS101S to execute the

corresponding interrupt service routine. This feature is useful for

systems that require a low power standby mode.

–9–REV. A

ADSP-TS101S

Clock Domains

As shown in Figure 4, the ADSP-TS101S has two clock inputs,

SCLK (system clock) and LCLK (local clock),

that drive its

two major clock domains:

• SCLK (system clock). Provides clock input for the

external bus interface and defines the ac specification

reference for the external bus signals. The external bus

interface runs at 1× the SCLK frequency. A DLL locks

internal SCLK to SCLK input.

• LCLK (local clock). Provides clock input to the internal

clock driver, CCLK, which is the internal clock for the

core, internal buses, memory, and link ports. The instruc-

tion execution rate is equal to CCLK. A PLL from LCLK

generates CCLK which is phase-locked. The LCLKRAT

pins define the clock multiplication of LCLK to CCLK

(see Table 4). The link port clock is generated from

CCLK via a software programmable divisor. RESET

must be asserted until LCLK is stable and within speci-

fication for at least 2 ms. This applies to power-up as well

as any dynamic modification of LCLK after power-up.

Dynamic modification may include LCLK going out of

specification as long as RESET is asserted.

Connecting SCLK and LCLK to the same clock source is a

requirement for the device. Using an integer clock multipli-

cation value provides predictable cycle-by-cycle operation, a

requirement of fault-tolerant systems and some multi-

processing systems.

Noninteger values are completely functional and acceptable for

applications that do not require predictable cycle-by-cycle

operation.

Output Pin Drive Strength Control

Pins CONTROLIMP2-0 and DS2-0 work together to control

the output drive strength of two groups of pins, the

Address/Data/Control pin group and the Link pin group.

CONTROLIMP2-0 independently configures the two pin

groups to the maximum drive strength or to a digitally controlled

drive strength that is selectable by the DS2-0 pins (see Table 13

on Page 17). If the digitally controlled drive strength is selected

for a pin group the DS2-0 pins determine one of eight strength

levels for that group (see Table 14 on Page 17). The drive

strength selected varies the slew rate of the driver. Drive strength

0 (DS2-0 = 000) is the weakest and slowest slew rate. Drive

strength 7 (DS2-0 = 111) is the strongest and fastest slew rate.

The stronger drive strengths are useful for high frequency

switching while the lower strengths may allow use of a relaxed

design methodology. The strongest drive strengths have a larger

di/dt and thus require more attention to signal integrity issues

such a ringing, reflections and coupling. Also a larger di/dt can

increase external supply rail noise, which impacts power supply

and power distribution design.

The drive strengths for the

EMU

CPA

, and

DPA

pins are not

controllable and are fixed to the maximum level.

For drive strength calculation, see

Output Drive Currents on

Page 31

Power Supplies

The ADSP-TS101S has separate power supply connections for

internal logic (V

), analog circuits (V

DD_A

), and I/O buffer

DD_IO

) power supply. The internal (V

) and analog (V

DD_A

)

supplies must meet the 1.2 V requirement. The I/O buffer

DD_IO

) supply must meet the 3.3 V requirement.

The analog supply (V

DD_A

) powers the clock generator PLLs. To

produce a stable clock, systems must provide a clean power

supply to power input V

DD_A

. Designs must pay critical attention

to bypassing the V

DD_A

supply.

The required power-on sequence for the DSP is to provide V

(and V

DD_A

) before V

DD_IO

Filtering Reference Voltage and Clocks

Figure 5 shows a possible circuit for filtering V

REF

, SCLK_N, and

LCLK_N. This circuit provides the reference voltage for the

switching voltage, system clock, and local clock references.

Development Tools

The ADSP-TS101S is supported with a complete set of

CROSSCORE™ software and hardware development tools,

including Analog Devices emulators and VisualDSP++™ devel-

opment environment. The same emulator hardware that

supports other TigerSHARC processors also fully emulates the

ADSP-TS101S.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler (which is based on an algebraic

syntax), an archiver (librarian/library builder), a linker, a loader,

a cycle-accurate instruction-level simulator, a C/C++ compiler,

and a C/C++ runtime library that includes DSP and mathemat-

ical functions. A key point for these tools is C/C++ code

Figure 4. Clock Domains

LCLKRATx

SCLK_P

LCLK_P

SPD BITS,

LCTLx REGISTER

EXTERNAL INTERFACE

CCLK

(INSTRUCTION RATE)

LxCLKOUT/LxCLKIN

(LINK PORT RATE)

DLL

PLL

DLL

/LR

Figure 5. V

REF

, SCLK_N, and LCLK_N Filter

DD_IO

REF

SCLK_N

LCLK_N

R2 C1 C2

R1: 2k⍀ SERIES RESISTOR

R2: 1.67k⍀ SERIES RESISTOR

C1: 1␮F CAPACITOR (SMD)

C2: 1nF CAPACITOR (HF SMD) PLACED CLOSE TO DSP’S PINS

CROSSCORE is a trademark of Analog Devices, Inc.

VisualDSP++ is a trademark of Analog Devices, Inc.

剩余43页未读，继续阅读

yuheqing

粉丝: 0
资源: 9

ADSP-TS101S：300MHz嵌入式处理器，全面数据手册

嵌入式系统/ARM技术中的基于ADSP-TS101S嵌入式系统的混合编程

基于ADSP-TS101S实现的雷达脉冲压缩

基于ADSP-TS101S嵌入式系统的混合编程

基于USB总线的ADSP-TS101S链路口加载

单片机与DSP中的基于ADSP-TS101S的雷达信号处理系统的实现

单片机与DSP中的基于ADSP-TS101S的自适应动目标显示系统设计

单片机与DSP中的基于ADSP-TS101S的超分辨测向算法硬件实现

单片机与DSP中的基于ADSP-TS101S的多芯片数字信号处理系统的实现方案

ADSP-TS101S TigerSHARC DSP硬件手册：新一代数字信号处理器

ADSP-TS101S嵌入式系统：混合编程策略

最新资源