ARMv8架构手册：ARM公司权威指南
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"ARM_V8架构手册"
ARM_v8架构是ARM公司推出的64位指令集架构，主要针对ARMv8-A架构 profile。该手册详细介绍了ARMv8架构的设计原理、指令集、处理器核心功能以及相关的编程模型。ARMv8-A是面向高性能计算和服务器市场的处理器架构，它扩展了之前的32位ARMv7架构，引入了AArch64状态（64位执行状态）和AArch32状态（32位兼容模式），以提供更广泛的地址空间和更高的计算能力。
手册中的内容可能包括以下几个关键知识点：
1. **体系结构概述**：ARMv8-A架构支持两种执行状态，即64位的AArch64状态和32位的AArch32状态。AArch64提供了新的指令集和寄存器布局，增强了并行处理能力，提高了性能。而AArch32状态则允许向后兼容之前的32位应用程序。
2. **指令集**：ARMv8-A引入了新的64位指令集ARM64，它在指令效率和代码密度上有所提升，同时也保留了部分32位指令集以保持兼容性。新的指令集增加了向量处理指令，用于加速多媒体和科学计算任务。
3. **寄存器**：在AArch64状态下，通用寄存器的数量从32个增加到64个，每个寄存器宽度为64位，这显著提升了并行运算能力。此外，还有专门的浮点寄存器和向量寄存器。
4. **内存管理**：ARMv8-A支持更大范围的虚拟地址空间，可以达到48位或更多，允许更大的应用程序和更高效的内存分配。它还包括改进的页表结构和内存保护机制，以提高安全性。
5. **多核与并发**：ARMv8-A架构设计考虑了多核处理器，支持同步多线程(SMT)和高级中断处理，以实现更高效的多任务处理和实时响应。
6. **安全特性**：ARMv8引入了TrustZone技术，这是一种硬件级别的安全解决方案，通过创建安全和非安全的执行环境来保护敏感数据和操作。
7. **虚拟化支持**：ARMv8-A提供了硬件虚拟化支持，使得在单个处理器上运行多个操作系统实例成为可能，这对于云服务和数据中心的应用非常关键。
8. **软件开发**：手册也会涵盖开发工具、调试接口、编译器优化以及针对ARMv8-A架构的编程指南。
9. **性能优化**：ARMv8-A架构允许开发者利用新的指令和硬件特性进行性能优化，例如使用向量运算和异步计算来提高程序运行速度。
10. **专利与许可**：文档中会强调，虽然提供了架构信息，但使用这些信息进行产品开发需要遵守ARM公司的知识产权政策，需要获得相应的授权。
此手册对于理解ARMv8-A架构的细节、开发高效64位ARM应用以及进行系统级软件设计至关重要。它是软件开发者、系统架构师和硬件工程师的重要参考资料。
Preface
About this manual
xvi Copyright © 2013-2015 ARM Limited. All rights reserved. ARM DDI 0487A.g
Non-Confidential - Beta ID070815
About this manual
This manual describes the ARM
®
architecture v8, ARMv8. The architecture describes the operation of an
ARMv8-A Processing element (PE), and this manual includes descriptions of:
• The two Execution states, AArch64 and AArch32.
• The instruction sets:
— In AArch32 state, the A32 and T32 instruction sets, that are compatible with earlier versions of the
ARM architecture.
— In AArch64 state, the A64 instruction set.
• The states that determine how a PE operates, including the current Exception level and Security state, and in
AArch32 state the PE mode.
• The Exception model.
• The interprocessing model, that supports transitioning between AArch64 state and AArch32 state.
• The memory model, that defines memory ordering and memory management. This manual covers a single
architecture profile, ARMv8-A, that defines a Virtual Memory System Architecture (VMSA).
• The programmers’ model, and its interfaces to System registers that control most PE and memory system
features, and provide status information.
• The Advanced SIMD and floating-point instructions, that provide high-performance:
— Single-precision and double-precision floating-point operations.
— Conversions between double-precision, single-precision, and half-precision floating-point values.
— Integer, single-precision floating-point, and in A64, double-precision vector operations in all
instruction sets.
— Double-precision floating-point vector operations in the A64 instruction set.
• The security model, that provides two security states to support secure applications.
• The virtualization model, that support the virtualization of Non-secure operation.
• The Debug architecture, that provides software access to debug features.
This manual gives the assembler syntax for the instructions it describes, meaning that it describes instructions in
textual form. However, this manual is not a tutorial for ARM assembler language, nor does it describe ARM
assembler language, except at a very basic level. To make effective use of ARM assembler language, read the
documentation supplied with the assembler being used.
This manual is organized into parts:
Part A Provides an introduction to the ARMv8-A architecture, and an overview of the AArch64 and
AArch32 Execution states.
Part B Describes the application level view of the AArch64 Execution state, meaning the view from EL0.
It describes the application level view of the programmers’ model and the memory model.
Part C Describes the A64 instruction set, that is available in the AArch64 Execution state. The descriptions
for each instruction also include the precise effects of each instruction when executed at EL0,
described as unprivileged execution, including any restrictions on its use, and how the effects of the
instruction differ at higher Exception levels. This information is of primary importance to authors
and users of compilers, assemblers, and other programs that generate ARM machine code.
Part D Describes the system level view of the AArch64 Execution state. It includes details of the System
registers, most of which are not accessible from EL0, and the system level view of the programmers’
model and the memory model. This part includes the description of self-hosted debug.
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