ARMv8架构手册：ARM公司权威指南

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"ARM_V8架构手册" ARM_v8架构是ARM公司推出的64位指令集架构，主要针对ARMv8-A架构 profile。该手册详细介绍了ARMv8架构的设计原理、指令集、处理器核心功能以及相关的编程模型。ARMv8-A是面向高性能计算和服务器市场的处理器架构，它扩展了之前的32位ARMv7架构，引入了AArch64状态（64位执行状态）和AArch32状态（32位兼容模式），以提供更广泛的地址空间和更高的计算能力。手册中的内容可能包括以下几个关键知识点： 1. **体系结构概述**：ARMv8-A架构支持两种执行状态，即64位的AArch64状态和32位的AArch32状态。AArch64提供了新的指令集和寄存器布局，增强了并行处理能力，提高了性能。而AArch32状态则允许向后兼容之前的32位应用程序。 2. **指令集**：ARMv8-A引入了新的64位指令集ARM64，它在指令效率和代码密度上有所提升，同时也保留了部分32位指令集以保持兼容性。新的指令集增加了向量处理指令，用于加速多媒体和科学计算任务。 3. **寄存器**：在AArch64状态下，通用寄存器的数量从32个增加到64个，每个寄存器宽度为64位，这显著提升了并行运算能力。此外，还有专门的浮点寄存器和向量寄存器。 4. **内存管理**：ARMv8-A支持更大范围的虚拟地址空间，可以达到48位或更多，允许更大的应用程序和更高效的内存分配。它还包括改进的页表结构和内存保护机制，以提高安全性。 5. **多核与并发**：ARMv8-A架构设计考虑了多核处理器，支持同步多线程(SMT)和高级中断处理，以实现更高效的多任务处理和实时响应。 6. **安全特性**：ARMv8引入了TrustZone技术，这是一种硬件级别的安全解决方案，通过创建安全和非安全的执行环境来保护敏感数据和操作。 7. **虚拟化支持**：ARMv8-A提供了硬件虚拟化支持，使得在单个处理器上运行多个操作系统实例成为可能，这对于云服务和数据中心的应用非常关键。 8. **软件开发**：手册也会涵盖开发工具、调试接口、编译器优化以及针对ARMv8-A架构的编程指南。 9. **性能优化**：ARMv8-A架构允许开发者利用新的指令和硬件特性进行性能优化，例如使用向量运算和异步计算来提高程序运行速度。 10. **专利与许可**：文档中会强调，虽然提供了架构信息，但使用这些信息进行产品开发需要遵守ARM公司的知识产权政策，需要获得相应的授权。此手册对于理解ARMv8-A架构的细节、开发高效64位ARM应用以及进行系统级软件设计至关重要。它是软件开发者、系统架构师和硬件工程师的重要参考资料。

Preface

About this manual

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About this manual

This manual describes the ARM

architecture v8, ARMv8. The architecture describes the operation of an

ARMv8-A Processing element (PE), and this manual includes descriptions of:

• The two Execution states, AArch64 and AArch32.

• The instruction sets:

— In AArch32 state, the A32 and T32 instruction sets, that are compatible with earlier versions of the

ARM architecture.

— In AArch64 state, the A64 instruction set.

• The states that determine how a PE operates, including the current Exception level and Security state, and in

AArch32 state the PE mode.

• The Exception model.

• The interprocessing model, that supports transitioning between AArch64 state and AArch32 state.

• The memory model, that defines memory ordering and memory management. This manual covers a single

architecture profile, ARMv8-A, that defines a Virtual Memory System Architecture (VMSA).

• The programmers’ model, and its interfaces to System registers that control most PE and memory system

features, and provide status information.

• The Advanced SIMD and floating-point instructions, that provide high-performance:

— Single-precision and double-precision floating-point operations.

— Conversions between double-precision, single-precision, and half-precision floating-point values.

— Integer, single-precision floating-point, and in A64, double-precision vector operations in all

instruction sets.

— Double-precision floating-point vector operations in the A64 instruction set.

• The security model, that provides two security states to support secure applications.

• The virtualization model, that support the virtualization of Non-secure operation.

• The Debug architecture, that provides software access to debug features.

This manual gives the assembler syntax for the instructions it describes, meaning that it describes instructions in

textual form. However, this manual is not a tutorial for ARM assembler language, nor does it describe ARM

assembler language, except at a very basic level. To make effective use of ARM assembler language, read the

documentation supplied with the assembler being used.

This manual is organized into parts:

Part A Provides an introduction to the ARMv8-A architecture, and an overview of the AArch64 and

AArch32 Execution states.

Part B Describes the application level view of the AArch64 Execution state, meaning the view from EL0.

It describes the application level view of the programmers’ model and the memory model.

Part C Describes the A64 instruction set, that is available in the AArch64 Execution state. The descriptions

for each instruction also include the precise effects of each instruction when executed at EL0,

described as unprivileged execution, including any restrictions on its use, and how the effects of the

instruction differ at higher Exception levels. This information is of primary importance to authors

and users of compilers, assemblers, and other programs that generate ARM machine code.

Part D Describes the system level view of the AArch64 Execution state. It includes details of the System

registers, most of which are not accessible from EL0, and the system level view of the programmers’

model and the memory model. This part includes the description of self-hosted debug.

Preface

About this manual

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Part E Describes the application level view of the AArch32 Execution state, meaning the view from the

EL0. It describes the application level view of the programmers’ model and the memory model.

Note

In AArch32 state, execution at EL0 is execution in User mode.

Part F Describes the T32 and A32 instruction sets, that are available in the AArch32 Execution state. These

instruction sets are backwards-compatible with earlier versions of the ARM architecture. This part

describes the precise effects of each instruction when executed in User mode, described as

unprivileged execution or execution at EL0, including any restrictions on its use, and how the effects

of the instruction differ at higher Exception levels. This information is of primary importance to

authors and users of compilers, assemblers, and other programs that generate ARM machine code.

Note

User mode is the only mode where software execution is unprivileged.

Part G Describes the system level view of the AArch32 Execution state, that is generally compatible with

earlier versions of the ARM architecture. This part includes details of the System registers, most of

which are not accessible from EL0, and the conceptual coprocessor interface to those registers. It

also describes the system level view of the programmers’ model and the memory model.

Part H Describes the Debug architecture for external debug. This provides configuration, breakpoint and

watchpoint support, and a Debug Communications Channel (DCC) to a debug host.

Part I Describes additional features of the architecture that are not closely coupled to a processing element

(PE), and therefore are accessed through memory-mapped interfaces. Some of these features are

OPTIONAL.

Appendixes Provide additional information. Some appendixes give information that is not part of the ARMv8

architectural requirements. The cover page of each appendix indicates its status.

Preface

Using this manual

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Using this manual

The information in this manual is organized into parts, as described in this section.

Part A, Introduction and Architecture Overview

Part A gives an overview of the ARMv8-A architecture profile, including its relationship to the other ARM PE

architectures. It introduces the terminology used to describe the architecture, and gives an overview of the

Executions states, AArch64 and AArch32. It contains the following chapter:

Chapter A1 Introduction to the ARMv8 Architecture

Read this for an introduction to the ARMv8 architecture.

Part B, The AArch64 Application Level Architecture

Part B describes the application level view of the architecture in AArch64 state. It contains the following chapters:

Chapter B1 The AArch64 Application Level Programmers’ Model

Read this for an application level description of the programmers’ model for software executing in

AArch64 state. It describes execution at EL0 when EL0 is using AArch64 state.

Chapter B2 The AArch64 Application Level Memory Model

Read this for an application level description of the memory model for software executing in

AArch64 state. It describes the memory model for execution in EL0 when EL0 is using AArch64

state. It includes information about ARM memory types, attributes, and memory access controls.

Part C, The A64 Instruction Set

Part C describes the A64 instruction set, that is used in AArch64 state. It contains the following chapters:

Chapter C1 The A64 Instruction Set

Read this for a description of the A64 instruction set and common instruction operation details.

Chapter C2 About the A64 Instruction Descriptions

Read this to understand the format of the A64 instruction descriptions.

Chapter C3 A64 Instruction Set Overview

Read this for an overview of the individual A64 instructions, that are divided into five functional

groups.

Chapter C4 A64 Instruction Set Encoding

Read this for a description of the A64 instruction set encoding.

Chapter C5 The A64 System Instruction Class

Read this for a description of the AArch64 system instructions and register descriptions, and the

system instruction class encoding space.

Chapter C6 A64 Base Instruction Descriptions

Read this for information on key aspects of the A64 base instructions and for descriptions of the

individual instructions, which are listed in alphabetical order.

Chapter C7 A64 Advanced SIMD and Floating-point Instruction Descriptions

Read this for information on key aspects of the A64 Advanced SIMD and floating-point instructions

and for descriptions of the individual instructions, which are listed in alphabetical order.

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Part D, The AArch64 System Level Architecture

Part D describes the AArch64 the system level view of the architecture. It contains the following chapters:

Chapter D1 The AArch64 System Level Programmers’ Model

Read this for a description of the AArch64 system level view of the programmers’ model.

Chapter D2 AArch64 Self-hosted Debug

Read this for an introduction to, and a description of, self-hosted debug in AArch64 state.

Chapter D3 The AArch64 System Level Memory Model

Read this for a description of the AArch64 system level view of the general features of the memory

system.

Chapter D4 The AArch64 Virtual Memory System Architecture

Read this for a system level view of the AArch64 Virtual Memory System Architecture (VMSA),

the memory system architecture of an ARMv8 implementation that is executing in AArch64 state.

Chapter D5 The Performance Monitors Extension

Read this for a description of an implementation of the ARM Performance Monitors, that are an

optional non-invasive debug component.

Chapter D6 The Generic Timer in AArch64 state

Read this for a description of an implementation of the AArch64 view of the ARM Generic Timer.

Chapter D7 AArch64 System Register Descriptions

Read this for an introduction to, and description of, each of the AArch64 system registers.

Part E, The AArch32 Application Level Architecture

Part E describes the AArch32 application level view of the architecture. It contains the following chapters:

Chapter E1 The AArch32 Application Level Programmers’ Model

Read this for an application level description of the programmers’ model for software executing in

AArch32 state. It describes execution at EL0 when EL0 is using AArch32 state.

Chapter E2 The AArch32 Application Level Memory Model

Read this for an application level description of the memory model for software executing in

AArch32 state. It describes the memory model for execution in EL0 when EL0 is using AArch32

state. It includes information about ARM memory types, attributes, and memory access controls.

Part F, The AArch32 Instruction Sets

Part F describes the T32 and A32 instruction sets, that are used in AArch32 state. It contains the following chapters:

Chapter F1 The AArch32 Instruction Sets Overview

Read this for an overview of the T32 and A32 instruction sets.

Chapter F2 About the T32 and A32 Instruction Descriptions

Read this to understand the format of the T32 and A32 instruction descriptions.

Chapter F3 T32 Base Instruction Set Encoding

Read this for an introduction to the T32 instruction set and a description of how the T32 instruction

set uses the ARM programmers’ model.

Chapter F4 A32 Base Instruction Set Encoding

Read this for a description of the A32 base instruction set encoding.

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Chapter F5 T32 and A32 Instruction Sets Advanced SIMD and floating-point Encodings

Read this for an overview of the T32 and A32 Advanced SIMD and floating-point instruction sets.

Chapter F6 T32 and A32 Base Instruction Set Instruction Descriptions

Read this for a description of each T32 and A32 base instruction.

Chapter F7 T32 and A32 Advanced SIMD and floating-point Instruction Descriptions

Read this for a description of each T32 and A32 Advanced SIMD and floating-point instruction.

Part G, The AArch32 System Level Architecture

Part G describes the AArch32 system level view of the architecture. It contains the following chapters:

Chapter G1 The AArch32 System Level Programmers’ Model

Read this for a description of the AArch32 system level view of the programmers’ model for

execution in an Exception level that is using AArch32.

Chapter G2 AArch32 Self-hosted Debug

Read this for an introduction to, and a description of, self-hosted debug in AArch64 state.

Chapter G3 The AArch32 System Level Memory Model

Read this for a system level view of the general features of the memory system.

Chapter G4 The AArch32 Virtual Memory System Architecture

Read this for a description of the AArch32 Virtual Memory System Architecture (VMSA).

Chapter G5 The Generic Timer in AArch32 state

Read this for a description of an implementation of the AArch32 view of the ARM Generic Timer.

Chapter G6 AArch32 System Register Descriptions

Read this for a description of each of the AArch32 system registers.

Part H, External Debug

Part H describes the architecture for external debug. It contains the following chapters:

Chapter H1 Introduction to External Debug

Read this for an introduction to external debug, and a definition of the scope of this part of the

manual.

Chapter H2 Debug State

Read this for a description of debug state, which the PE might enter as the result of a Halting debug

event.

Chapter H3 Halting Debug Events

Read this for a description of the external debug events referred to as Halting debug events.

Chapter H4 The Debug Communication Channel and Instruction Transfer Register

Read this for a description of the communication between a debugger and the PE debug logic using

the Debug Communications Channel and the Instruction Transfer register.

Chapter H5 The Embedded Cross-Trigger Interface

Read this for a description of the embedded cross-trigger interface.

Chapter H6 Debug Reset and Powerdown Support

Read this for a description of reset and powerdown support in the Debug architecture.

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