STM32L4系列微处理器：低功耗与强大功能详解

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STM32L4系列微处理器硬件手册提供了对STM32L4R5xx、STM32L4R7xx和STM32L4R9xx这一高性能低功耗微控制器的深入理解。该手册详细阐述了这些微处理器的关键特性和技术规格，适用于已经进入量产阶段的产品。首先，这些处理器基于Arm Cortex-M4内核，配备了浮点单元(FPU)，能够实现高效的计算性能，支持高达120MHz的工作频率。其核心功能包括0-wait-state执行能力，这意味着从闪存直接访问数据时，处理器可以几乎无延迟地运行。此外，它还具有适应性实时加速器(ART Accelerator)，有助于提高任务处理效率。在功耗管理方面，STM32L4系列表现出色。它们支持FlexPowerControl，可以在1.71V到3.6V的电压范围内工作，确保在宽温度范围内(-40°C至85/125°C)保持稳定性能。在待机模式下，功耗极低，比如在VBAT模式下仅需305nA，足以维持RTC和备份寄存器的供电。同时，提供多种节能模式如Shutdown、Standby以及带有RTC的更低功耗状态，比如Stop2模式下的2.8μA/MHz和Run模式下的110μA/MHz和43μA/MHz，展示了出色的能效平衡。对于存储容量，STM32L4系列配备有高达2MB的Flash存储器和640KB的SRAM，能满足许多嵌入式应用的需求。此外，它们还支持多种接口，如LCD-TFT和MIP IDSI，便于与外部设备连接和显示控制。性能基准测试表明，STM32L4系列在Dhrystone 2.1基准测试中的每兆赫兹性能达到1.25DMIPS，而Coremark测试结果则显示出强大的核心处理能力，达到409.20 Coremark单位（在120MHz频率下为3.41 Coremark/MHz）。 STM32L4R5xx、STM32L4R7xx和STM32L4R9xx微处理器是设计高能效、灵活且功能丰富的嵌入式系统解决方案的理想选择，它们在低功耗、高性能和广泛的接口支持上达到了业界领先水平。通过阅读这份硬件手册，开发人员可以全面了解如何优化设计并充分利用这些微处理器的潜力。

Description STM32L4R5xx, STM32L4R7xx and STM32L4R9xx

16/310 DS12023 Rev 4

LCD - TFT No Yes No Yes No Yes

MIPI DSI Host

(2)

No Yes No Yes No Yes

Random number

generator

Yes

GPIOs

(3)

Wakeup pins

Nb of I/Os down to

1.08 V

110

115

112

140

131

Capacitive sensing

Number of channels

21 18 24

12-bit ADCs

Number of channels

16 14 16 14

12-bit DAC

Number of channels

Internal voltage

reference buffer

Yes

Analog comparator 2

Operational amplifiers 2

Max. CPU frequency 120 MHz

Operating voltage

)

1.71 to 3.6 V

Operating voltage

DD12

)

1.05 to 1.32 V

Operating temperature Ambient operating temperature: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C

Packages

LQFP100 UFBGA132

LQFP144

WLCSP144

LQFP144

LQFP144,

UFBGA144

WLCSP144

UFBGA169

1. For the LQFP100 package, only FMC bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory

using the NE1 chip select.

2. The DSI Host interface is only available on the STM32L4R9xx sales types.

3. In the case of an external SMPS package type is used, 2 GPIOs are replaced by V

DD12

pins to connect the SMPS power

supplies hence reducing the number of available GPIOs by 2.

Table 2. STM32L4R5xx, STM32L4R7xx and STM32L4R9xx

features and peripheral counts (continued)

Peripheral

R5VI

R5VG

R7VI

R9VI

R9VG

R5QI

R5QG

R5ZI

R5ZG

R7ZI

R9ZI

R9ZG

R5AI

R5AG

R7AI

R9AI

R9AG

DS12023 Rev 4 17/310

STM32L4R5xx, STM32L4R7xx and STM32L4R9xx Description

Figure 1. STM32L4R5xx, STM32L4R7xx and STM32L4R9xx block diagram

Note: AF: alternate function on I/O pins.

MSv49327V1

USB

OTG

Flash

up to

2 MB

Flexible static memory controller (FSMC):

SRAM, PSRAM, NOR Flash, NAND Flash

GPIO PORT A

AHB/APB2

EXT IT. WKUP

114 AF

PA[15:0]

TIM1 / PWM

3 compl. channels (TIM1_CH[1:3]N),

4 channels (TIM1_CH[1:4]),

ETR, BKIN, BKIN2 as AF

USART1

RX, TX, CK,CTS,

RTS as AF

SPI1

MOSI, MISO,

SCK, NSS as AF

APB260 M Hz

APB1 30MHz

MOSI, MISO, SCK, NSS as AF

DAC1_OUT

ITF

WWDG

RTC_TS

OSC32_IN

OSC32_OUT

VDDA, VSSA

VDD, VSS, NRST

smcard

irDA

16b

SDIO / MMC

D[7:0]

CMD, CK as AF

VBAT = 1.55 to 3.6 V

SCL, SDA, SMBA as AF

JTAG & SW

ARM Cortex-M4

120 MHz

FPU

NVIC

ETM

MPU

TRACECLK

TRACED[3:0]

DMA2

ART

ACCEL/

CACHE

CLK, NE[4:1], NL, NBL[1:0],

A[25:0], D[15:0], NOE, NWE,

NWAIT, NCE, INT as AF, FRAM

RNG

ID, VBUS, SOF

FIFO

@ VDDA

BOR

Supply

supervision

PVD, PVM

Int

reset

XTAL 32 kHz

MAN AGT

RTC

FCLK

Standby

interface

IWDG

@VBAT

@ VDD

@VDD

AWU

Reset & clock

control

PCLKx

VDD = 1.71 to 3.6 V

VSS

Voltage

regulator

3.3 to 1.2 V

VDD

Power management

@ VDD

RTC_TAMPx

Backup register

AHB bus-matrix

TIM15

2 channels,

1 compl. channel, BKIN as AF

DAC1

DAC2

TIM6

TIM7

TIM2

TIM3

TIM4

TIM5

USART2

USART3

I2C1/SMBUS

D-BUS

APB1 120 MHz (max)

SRAM 192 KB

SRAM 64 KB

NJTRST, JTDI,

JTCK/SWCLK

JTDO/SWD, JTDO

I-BUS

S-BUS

DMA1

PB[15:0]

PC[15:0]

PD[15:0]

PE[15:0]

PF[15:0]

PG[15:0]

PH[15:0]

GPIO PORT B

GPIO PORT C

GPIO PORT D

GPIO PORT E

GPIO PORT F

GPIO PORT G

GPIO PORT H

TIM8 / PWM

16b

TIM16

16b

TIM17

16b

3 compl. Channels (TIM1_CH[1:3]N),

4 channels (TIM1_CH[1:4]),

ETR, BKIN, BKIN2 as AF

1 channel,

1 compl. channel, BKIN as AF

1 channel,

1 compl. channel, BKIN as AF

DAC2_OUT

16b

SCL, SDA, SMBA as AF

MOSI, MISO, SCK, NSS as AF

RX, TX, CTS, RTS as AF

RX, TX, CK, CTS, RTS as AF

smcard

irDA

smcard

irDA

32b

16b

32b

4 channels, ETR as AF

AHB/APB1

OSC_IN

OSC_OUT

HCLKx

XTAL OSC

4- 16MHz

8 analog inputs common to the ADC

VREF+

USAR T 2MBps

Temperature sensor

SAI1

MCLK_A, SD_A, FS_A, SCK_A, EXTCLK

MCLK_B, SD_B, FS_B, SCK_B as AF

SAI2

MCLK_A, SD_A, FS_A, SCK_A, EXTCLK

MCLK_B, SD_B, FS_B, SCK_B as AF

DFSDM

SDCKIN[7:0], SDDATIN[7:0],

SDCKOUT,SDTRIG as AF

Touch sensing controller

8 Groups of 4 channels max as AF

OUT, INN, INP

LPUART1

LPTIM1

LPTIM2

RX, TX, CTS, RTS as AF

IN1, IN2, OUT, ETR as AF

IN1, OUT, ETR as AF

RC HSI

RC LSI

PLL 1&2&3

MSI

Octo SPI1 memory interface

IO[7:0],

CLK, NCS. DQS

@ VDDUSB

COMP1

INP, INN, OUT

COMP2

INP, INN, OUT

@ VDDA

RTC_OUT

VDDIO, VDDUSB

FIFO

PHY

AHB1 120 MHz

CRC

OUT, INN, INP

I2C2/SMBUS

I2C3/SMBUS

OpAmp1

SPI3

SPI2

UART5

UART4

APB2 120MHz

AHB2 120 MHz

OpAmp2

@VDDA

Firewall

VREF Buffer

@ VDDA

@ VDD

Camera Interface

FIFO

HSYNC, VSYNC,

PIXCLK, D[13:0]

CHROM-ART

DMA2D

FIFO

PI[11:0]

GPIO PORT I

FIFO

TX, RX as AF

bxCAN1

SCL, SDA, SMBA as AF

I2C4/SMBUS

Octo SPI2 memory interface

FIFO

LCD - TFT

SRAM 384 KB

ITF

ADC1

@ VDDA

DSI Host

DSI

PHI

DSI_D0 P/N

DSI_D1 P/N

DSI_CK P/N

VDD12DSI, VDDSI, VSSDSI

VCAPDSI

DSI_TE

LCD_R[7:0], LCD_G[7:0], LCD_B[7:0],

LCD_HSYNC, LCD_VSYNC, LCD_DE,

LCD_CLK

Chrom-GRC

(GFXMMU)

FIFO

Functional overview STM32L4R5xx, STM32L4R7xx and STM32L4R9xx

18/310 DS12023 Rev 4

3 Functional overview

3.1 Arm

Cortex

-M4 core with FPU

The Arm

Cortex

-M4 with FPU processor is the latest generation of Arm

processors for

embedded systems. It was developed to provide a low-cost platform that meets the needs of

the MCU implementation, with a reduced pin count and with low-power consumption, while

delivering outstanding computational performance and an advanced response to interrupts.

The Arm

Cortex

-M4 with FPU 32-bit RISC processor features an exceptional code-

efficiency, delivering the expected high-performance from an Arm

core in a memory size

usually associated with 8-bit and 16-bit devices.

The processor supports a set of DSP instructions which allows an efficient signal processing

and a complex algorithm execution. Its single precision FPU speeds up the software

development by using metalanguage development tools to avoid saturation.

With its embedded Arm

core, the STM32L4Rxxx family is compatible with all Arm

tools

and software.

Figure 1 shows the general block diagram of the STM32L4Rxxx family devices.

3.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator that is optimized for the STM32 industry-

standard Arm

Cortex

-M4 processors. It balances the inherent performance advantage of

the Arm

Cortex

-M4 over Flash memory technologies, which normally requires the

processor to wait for the Flash memory at higher frequencies.

To release the processor near 150 DMIPS performance at 120 MHz, the accelerator

implements an instruction prefetch queue and a branch cache, which increases the

program’s execution speed from the Flash memory. Based on CoreMark benchmark, the

performance achieved thanks to the ART accelerator is equivalent to 0 wait state program

execution from the Flash memory at a CPU frequency of up to 120

MHz.

3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to the memory

and to prevent one task to accidentally corrupt the memory or the resources used by any

other active task. This memory area is organized into up to eight protected areas, which can

be divided in up into eight subareas each. The protection area sizes range between 32

bytes and the whole 4 gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be

protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-

time operating system). If a program accesses a memory location that is prohibited by the

MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can

dynamically update the MPU area setting based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

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