Arm
®
Cortex
®
‑A715 Core Technical Reference Manual
Document ID: 101590_0102_08_en
Issue: 08
Contents
B.5.9 TRCIDR0, External ID Register 0....................................................................................................... 608
B.5.10 TRCIDR1, External ID Register 1.....................................................................................................610
B.5.11 TRCIDR2, External ID Register 2.....................................................................................................612
B.5.12 TRCIDR3, External ID Register 3.....................................................................................................613
B.5.13 TRCIDR4, External ID Register 4.....................................................................................................616
B.5.14 TRCIDR5, External ID Register 5.....................................................................................................618
B.5.15 TRCIDR6, External ID Register 6.....................................................................................................619
B.5.16 TRCIDR7, External ID Register 7.....................................................................................................621
B.5.17 TRCITCTRL, Integration Mode Control Register.......................................................................... 622
B.5.18 TRCCLAIMSET, External Claim Tag Set Register..........................................................................623
B.5.19 TRCCLAIMCLR, External Claim Tag Clear Register..................................................................... 625
B.5.20 TRCDEVARCH, External Device Architecture Register.............................................................. 627
B.5.21 TRCDEVID2, Device Configuration Register 2.............................................................................629
B.5.22 TRCDEVID1, Device Configuration Register 1.............................................................................630
B.5.23 TRCDEVID, External Device Configuration Register...................................................................631
B.5.24 TRCDEVTYPE, Device Type Register..............................................................................................633
B.5.25 TRCPIDR4, Peripheral Identification Register 4............................................................................634
B.5.26 TRCPIDR5, Peripheral Identification Register 5............................................................................636
B.5.27 TRCPIDR6, Peripheral Identification Register 6............................................................................637
B.5.28 TRCPIDR7, Peripheral Identification Register 7............................................................................638
B.5.29 TRCPIDR0, Peripheral Identification Register 0............................................................................639
B.5.30 TRCPIDR1, Peripheral Identification Register 1............................................................................641
B.5.31 TRCPIDR2, Peripheral Identification Register 2............................................................................642
B.5.32 TRCPIDR3, Peripheral Identification Register 3............................................................................644
B.5.33 TRCCIDR0, Component Identification Register 0........................................................................645
B.5.34 TRCCIDR1, Component Identification Register 1........................................................................646
B.5.35 TRCCIDR2, Component Identification Register 2........................................................................648
B.5.36 TRCCIDR3, Component Identification Register 3........................................................................649
B.6 External ROM table registers summary............................................................................................... 650
B.6.1 ROMENTRY0, Class 0x9 ROM Table Entries..................................................................................651
B.6.2 ROMENTRY1, Class 0x9 ROM Table Entries..................................................................................653
B.6.3 ROMENTRY2, Class 0x9 ROM Table Entries..................................................................................655
B.6.4 ROMENTRY3, Class 0x9 ROM Table Entries..................................................................................657
B.6.5 AUTHSTATUS, Authentication Status Register...............................................................................659
B.6.6 DEVARCH, Device Architecture Register.........................................................................................660
B.6.7 PIDR4, Peripheral Identification Register 4......................................................................................661
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