ARMv8-A架构指南：Cortex-A系列处理器

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"本文档是ARM Cortex-A系列的程序员指南，专注于ARMv8-A架构，详细介绍了该架构的指令集和寄存器定义等关键内容。由ARM公司于2015年发布，包含了版本1.0的更新信息。" 在深入探讨ARMv8架构之前，首先要理解它的重要性。ARM架构是一种广泛应用于移动设备、服务器和嵌入式系统的处理器架构，以其低功耗和高效性能而闻名。ARMv8-A是ARM架构的一个主要版本，引入了64位计算能力，是Cortex-A系列处理器的基础。 **ARMv8-A架构概述** ARMv8-A架构的主要特征是引入了两种执行状态：Aarch64（64位）和Aarch32（32位）。Aarch64提供了全新的指令集，称为AArch64状态，增强了处理能力和效率，尤其是在大规模数据处理和多任务环境中。同时，Aarch32状态则保持了与前一代ARMv7-A架构的向后兼容性，确保软件的平滑过渡。 **指令集** ARMv8-A的指令集扩展了原有的ARM指令集，增加了更多用于64位操作的新指令。这些新指令包括数据处理、浮点运算、分支和跳转、内存访问等，旨在提升处理器的计算性能和能效。此外，还包括对向量处理的支持，适合高性能计算和图形处理。 **寄存器系统** 在ARMv8-A中，寄存器系统进行了重大改进。64位模式下，通用寄存器的数量从16个增加到32个，每个寄存器都是64位宽，这显著提高了并行处理能力。浮点寄存器也进行了扩展，提供更强大的单精度和双精度浮点运算支持。 **内存模型** ARMv8-A架构采用了一种名为"Load-Acquire/Store-Release"的内存一致性模型，以支持多核处理器间的并发操作。这种模型确保了在多线程环境中的正确数据同步，是现代高性能和多核处理器设计的关键特性。 **安全性与虚拟化** ARMv8-A还引入了硬件级别的安全扩展（如TrustZone技术），以及增强的虚拟化支持（如Hypervisor模式），使得设备能够更安全地运行多个操作系统实例，提高了系统的隔离性和安全性。 **中断和异常处理** 中断和异常处理机制在ARMv8-A中得到了优化，允许处理器更高效地响应外部事件，如硬件中断或软件触发的异常，这对于实时系统和高可用性环境至关重要。 **总结** ARMv8-A架构是ARM公司在处理器设计上的一个重要里程碑，其64位指令集、增强的寄存器系统、优化的内存模型以及安全和虚拟化特性，都极大地提升了处理器的性能和应用范围。对于开发者而言，理解和掌握ARMv8-A架构是开发高效、可靠的ARM平台软件的关键。

ID050815 Non-Confidential

Chapter 1

Introduction

ARMv8-A is the latest generation of the ARM architecture that is targeted at the Applications

Profile. In this book, the name ARMv8 is used to describe the overall architecture, which now

includes both 32-bit execution and 64-bit execution states. ARMv8 introduces the ability to

perform execution with 64-bit wide registers, but provides mechanisms for backwards

compatibility to enable existing ARMv7 software to be executed.

AArch64 is the name used to describe the 64-bit execution state of the ARMv8 architecture.

AArch32 describes the 32-bit execution state of the ARMv8 architecture, which is almost

identical to ARMv7. GNU and Linux documentation (except for Redhat and Fedora

distributions) sometimes refers to AArch64 as ARM64.

Because many of the concepts of the ARMv8-A architecture are shared with the ARMv7-A

architecture, the details of all those concepts are not covered here. As a general introduction to

the ARMv7-A architecture, refer to the ARM

Cortex

-A Series Programmer’s Guide. This

guide can also help you to familiarize yourself with some of the concepts discussed in this

volume. However, the ARMv8-A architecture profile is backwards compatible with earlier

iterations, like most versions of the ARM architecture. Therefore, there is a certain amount of

overlap between the way the ARMv8 architecture and previous architectures function. The

general principles of the ARMv7 architecture are only covered to explain the differences

between the ARMv8 and earlier ARMv7 architectures.

Cortex-A series processors now include both ARMv8-A and ARMv7-A implementations:

• The Cortex-A5, Cortex-A7, Cortex-A8, Cortex-A9, Cortex-A15, and Cortex-A17

processors all implement the ARMv7-A architecture.

• The Cortex-A53 and Cortex-A57 processors implement the ARMv8-A architecture.

Introduction

ID050815 Non-Confidential

ARMv8 processors still support software (with some exceptions) written for the ARMv7-A

processors. This means, for example, that 32-bit code written for the ARMv7 Cortex-A series

processors also runs on ARMv8 processors such as the Cortex-A57. However, the code will

only run when the ARMv8 processor is in the AArch32 execution state. The A64 64-bit

instruction set, however, does not run on ARMv7 processors, and only runs on the ARMv8

processors.

Some knowledge of the C programming language and microprocessors is assumed of the

readers of this book. There are pointers to further reading, referring to books and websites that

can give you a deeper level of background to the subject matter.

The change from 32-bit to 64-bit

There are several performance gains derived from moving to a 64-bit processor.

• The A64 instruction set provides some significant performance benefits, including a

larger register pool. The additional registers and the ARM Architecture Procedure Call

Standard (AAPCS) provide a performance boost when you must pass more than four

registers in a function call. On ARMv7, this would require using the stack, whereas in

AArch64 up to eight parameters can be passed in registers.

• Wider integer registers enable code that operates on 64-bit data to work more efficiently.

A 32-bit processor might require several operations to perform an arithmetic operation on

64-bit data. A 64-bit processor might be able to perform the same task in a single

operation, typically at the same speed required by the same processor to perform a 32-bit

operation. Therefore, code that performs many 64-bit sized operations is significantly

faster.

• 64-bit operation enables applications to use a larger virtual address space. While the Large

Physical Address Extension (LPAE) extends the physical address space of a 32-bit

processor to 40-bit, it does not extend the virtual address space. This means that even with

LPAE, a single application is limited to a 32-bit (4GB) address space. This is because

some of this address space is reserved for the operating system.

• Software running on a 32-bit architecture might need to map some data in or out of

memory while executing. Having a larger address space, with 64-bit pointers, avoids this

problem. However, using 64-bit pointers does incur some cost. The same piece of code

typically uses more memory when running with 64-pointers than with 32-bit pointers.

Each pointer is stored in memory and requires eight bytes instead of four. This might

sound trivial, but can add up to a significant penalty. Furthermore, the increased usage of

memory space associated with a move to 64-bits can cause a drop in the number of

accesses that hit in the cache. This in turn can reduce performance.

The larger virtual address space also enables memory-mapping larger files. This is the

mapping of the file contents into the memory map of a thread. This can occur even though

the physical RAM might not be large enough to contain the whole file.

Introduction

ID050815 Non-Confidential

1.1 How to use this book

This book provides a single guide for programmers who want to use the Cortex-A series

processors that implement the ARMv8 architecture. The guide brings together information from

a wide variety of sources that is useful to both ARM assembly language and C programmers. It

is meant to complement rather than replace other ARM documentation available for ARMv8

processors. The other documents for specific information includes the ARM Technical

Reference Manuals (TRMs) for the processors themselves, documentation for individual

devices or boards or, most importantly, the ARM Architecture Reference Manual - ARMv8, for

ARMv8-A architecture profile - the ARM ARM.

This book is not written at an introductory level. It assumes some knowledge of the C

programming language and microprocessors. Hardware concepts such as caches and Memory

Management Units are covered, but only where this knowledge is valuable to the application

writer. The book looks at the way operating systems utilize ARMv8 features, and how to take

full advantage of the capabilities of the ARMv8 processors. Some chapters contain pointers to

additional reading. We also refer to books and web sites that can give a deeper level of

background to the subject matter, but often the main focus is the ARM-specific detail. No

assumptions are made on the use of any particular toolchain, and both GNU and ARM tools are

mentioned throughout the book.

If you are new to the ARMv8 architecture, Chapter 2 ARMv8-A Architecture and Processors

describes the previous 32-bit ARM architectures, introduces ARMv8, and describes some of the

properties of the ARMv8 processors. Next, Chapter 3 Fundamentals of ARMv8 describes the

building blocks of the architecture in the form of Exception levels and Execution states.

Chapter 4 ARMv8 Registers then describes the registers available to you in the ARMv8

architecture.

One of the most significant changes introduced in the ARMv8 architecture is the addition of a

64-bit instruction set, which complements the existing 32-bit architecture. Chapter 5 An

Introduction to the ARMv8 Instruction Sets describes the differences between the Instruction Set

Architecture (ISA) of ARMv7 (A32), and that of the A64 instruction set. Chapter 6 The A64

instruction set looks at the Instruction Set and its use in more detail. In addition to a new

instruction set for general operation, ARMv8 also has a changed NEON and floating-point

instruction set. Chapter 7 AArch64 Floating-point and NEON describes the changes in ARMv8

to ARM Advanced SIMD (NEON) and floating-point instructions. For a more detailed guide to

NEON and its capabilities at ARMv7, refer to the ARM

NEON

™

Programmer’s Guide.

Chapter 8 Porting to A64 of this book covers the problems you might encounter when porting

code from other architectures, or previous ARM architectures to ARMv8. Chapter 9 The ABI

for ARM 64-bit Architecture describes the Application Binary Interface (ABI) for the ARM

architecture specification. The ABI is a specification for all the programming behavior of an

ARM target, which governs the form your 64-bit code takes. Chapter 10 AArch64 Exception

Handling describes the exception handling behavior of ARMv8 in AArch64 state.

Following this, the focus moves to the internal architecture of the processor. Chapter 11 Caches

describes the design of caches and how the use of caches can improve performance.

An important motivating factor behind ARMv8 and moving to a 64-bit architecture is

potentially enabling access to larger address space than is possible using just 32 bits. Chapter 12

The Memory Management Unit describes how the MMU converts virtual memory addresses to

physical addresses.

Chapter 13 Memory Ordering describes the weakly-ordered model of memory in the ARMv8

architecture. Generally, this means that the order of memory accesses is not required to be the

same as the program order for load and store operations. Only some programmers must be aware

of memory ordering issues. If your code interacts directly with the hardware or with code

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