CLRC632 14443 RFID Reader: Functionality, Specifications & Compatibility

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CLRC632是一款专为13.56MHz无接触通信设计的集成电路(IC)，它在智能卡识别领域提供了高效能的调制解调功能，适用于多种MIFARE产品系列，包括MIFARE Mini、MIFARE 1K、MIFARE 4K和MIFARE Ultralight，这些产品在文档中统称为MIFARE。这款IC的主要特点包括： 1. 卓越的调制和解调技术：CLRC632采用先进的技术确保了与被动式无接触卡片进行高效、稳定的通信，这对于各类近距离通信应用至关重要。 2. 广泛的协议支持：它兼容ISO/IEC 14443 A和B标准的所有协议层，这意味着它可以与各种符合该标准的设备无缝交互，只要外部组件如振荡器、电源和天线等正确配置。 3. 小型化和集成度：CLRC632的设计紧凑，占用空间小，这使得它在小型设备上易于集成，降低了系统成本和复杂性。 4. 兼容性：它与MFRC500、MFRC530、MFRC531和SLRC400等其他同类产品具有引脚兼容性，使得开发人员可以轻松地在现有设计中替换或升级到CLRC632。 5. 通用性：为了提高文档的易读性，对不同类型的MIFARE产品和协议采用了统一的命名，方便开发者理解和操作。 6. 标准化接口：为了实现高效通信，用户必须确保使用标准的接口和遵循规范，以充分利用CLRC632的全部性能。在进行系统设计时，设计师需要了解CLRC632的具体电气规格，如数据传输速率、功耗特性、抗干扰能力等，以便根据具体应用需求进行精确配置。此外，可能还需要考虑电源管理、错误检测和纠正机制，以及如何处理不同协议的帧结构和命令响应。 CLRC632是一个高度灵活且性能卓越的14443读写器，适用于广泛的应用场景，如公共交通、门禁系统、电子支付等，但其实际效能取决于系统设计的完整性与合规性。通过充分理解并利用其特性和要求，可以极大地提升无接触通信系统的稳定性和用户体验。

Product data sheet

COMPANY PUBLIC

Rev. 3.7 — 27 February 2014

073937 16 of 127

NXP Semiconductors

CLRC632

Standard multi-protocol reader solution

9.2.2.3 Register initialization file (read/write)

The EEPROM memory content from block address 3 to 7 can initialize register sub

addresses 10h to 2Fh when the LoadConfig command is executed (see Section 11.5.1 on

page 95). This command requires the EEPROM starting byte address as a two byte

argument for the initialization procedure.

The byte assignment is shown in Table 16

The register initialization file is large enough to hold values for two initialization sets and

up to one block (16-byte) of user data. The startup configuration could be adapted to the

I-CODE1 StartUp configuration and stored in register block address 3 and 4, providing

additional flexibility.

Remark: The register initialization file can be read/written by users and these bytes can

be used to store other user data.

After each power-up, the default configuration enables the MIFARE and ISO/IEC 14443 A

protocol.

9.2.2.4 Content of I-CODE1 and ISO/IEC 15693 StartUp register values

Table 17

gives an overview of the StartUp values for I-CODE1 and ISO/IEC 15693

communication.

Table 16. Byte assignment for register initialization at startup

EEPROM byte address Register address Remark

EEPROM starting byte address 10h skipped

EEPROM + 1 starting byte address 11h copied

……

EEPROM + 31 starting byte address 2Fh copied

Product data sheet

COMPANY PUBLIC

Rev. 3.7 — 27 February 2014

073937 17 of 127

NXP Semiconductors

CLRC632

Standard multi-protocol reader solution

Table 17. Content of I-CODE1 startup configuration

EEPROM

byte

address

Value Symbol Description

30h 10h 00h Page free for user

31h 11h 58h TxControl transmitter pins TX1 and TX2 switched off, bridge driver

configuration, modulator driven from internal digital circuitry

32h 12h 3Fh CwConductance source resistance (R

) of TX1 and TX2 to minimum

33h 13h 05h ModGsCfgh source resistance (R

) of TX1 and TX2 at the time of

modulation, to determine the modulation index

34h 14h 2Ch CoderControl selects the bit coding mode and the framing during

transmission

35h 15h 3Fh ModWidth pulse width for code used (1 out of 256, NRZ or 1 out of 4)

pulse coding is set to standard configuration

36h 16h 3Fh ModWidthSOF pulse width of SOF

37h 17h 00h TypeBFraming -

38h 18h 00h Page free for user

39h 19h 8Bh RxControl1 amplifier gain is maximum

3Ah 1Ah 00h DecoderControl bit-collisions always evaluate to HIGH in the data bit stream

3Bh 1Bh 54h BitPhase BitPhase[7:0] is set to standard configuration

3Ch 1Ch 68h RxThreshold: MinLevel[3:0] and CollLevel[3:0] are set to maximum

3Dh 1Dh 00h BPSKDemControl -

3Eh 1Eh 41h RxControl2 use Q-clock for the receiver, automatic receiver off is

switched on, decoder is driven from internal analog circuitry

3Fh 1Fh 00h ClockQControl automatic Q-clock calibration is switched on

40h 20h 00h Page free for user

41h 21h 08h RxWait frame guard time is set to eight bit-clocks

42h 22h 0Ch ChannelRedundancy channel redundancy is set using I-CODE1

43h 23h FEh CRCPresetLSB CRC preset value is set using I-CODE1

44h 24h FFh CRCPresetMSB CRC preset value is set using I-CODE1

45h 25h 00h TimeSlot Period defines the time for the I-CODE1 time slots

46h 26h 00h MFOUTSelect pin MFOUT is set LOW

47h 27h 00h PreSet27 -

48h 28h 00h Page free for user

49h 29h 3Eh FIFOLevel WaterLevel[5:0] FIFO buffer warning level is set to standard

configuration

4Ah 2Ah 0Bh TimerClock TPreScaler[4:0] is set to standard configuration, timer unit

restart function is switched off

4Bh 2Bh 02h TimerControl Timer is started at the end of transmission, stopped at the

beginning of reception

4Ch 2Ch 00h TimerReload the timer unit preset value is set to standard configuration

4Dh 2Dh 02h IRQPinConfig pin IRQ is set to high-impedance

4Eh 2Eh 00h PreSet2E -

4Fh 2Fh 00h PreSet2F -

Product data sheet

COMPANY PUBLIC

Rev. 3.7 — 27 February 2014

073937 18 of 127

NXP Semiconductors

CLRC632

Standard multi-protocol reader solution

9.2.3 Crypto1 keys (write only)

MIFARE security requires specific cryptographic keys to encrypt data stream

communication on the contactless interface. These keys are called Crypto1 keys.

9.2.3.1 Key format

Keys stored in the EEPROM are written in a specific format. Each key byte must be split

into lower four bits k0 to k3 (lower nibble) and the higher four bits k4 to k7 (higher nibble).

Each nibble is stored twice in one byte and one of the two nibbles is bit-wise inverted. This

format is a precondition for successful execution of the LoadKeyE2 (see Section 11.7.1 on

page 97) and LoadKey commands (see Section 11.7.2 on page 97).

Using this format, 12 bytes of EEPROM memory are needed to store a 6-byte key. This is

shown in Figure 7

Example: The value for the key must be written to the EEPROM.

• If the key was: A0h A1h A2h A3h A4h A5h then

• 5Ah F0h 5Ah E1h 5Ah D2h 5Ah C3h 5Ah B4h 5Ah A5h would be written.

Remark: It is possible to load data for other key formats into the EEPROM key storage

location. However, it is not possible to validate card authentication with data which will

cause the LoadKeyE2 command (see Section 11.7.1 on page 97

) to fail.

9.2.3.2 Storage of keys in the EEPROM

The CLRC632 reserves 384 bytes of memory in the EEPROM for the Crypto1 keys. No

memory segmentation is used to mirror the 12-byte structure of key storage. Thus, every

byte of the dedicated memory area can be the start of a key.

Example: If the key loading cycle starts at the last byte address of an EEPROM block, (for

example, key byte 0 is stored at 12Fh), the next bytes are stored in the next EEPROM

block, for example, key byte 1 is stored at 130h, byte 2 at 131h up to byte 11 at 13Ah.

Based on the 384 bytes of memory and a single key needing 12 bytes, then up to 32

different keys can be stored in the EEPROM.

Remark: It is not possible to load a key exceeding the EEPROM byte location 1FFh.

Fig 7. Key storage format

001aak640

0 (LSB)Master key byte

Master key bits

EEPROM byte

address

Example

k7 k6 k5 k4 k7 k6 k5 k4

5Ah

k3 k2 k1 k0 k3 k2 k1 k0

n + 1

F0h

k7 k6 k5 k4 k7 k6 k5 k4

n + 2

5Ah

k3 k2 k1 k0 k3 k2 k1 k0

n + 3

E1h

5 (MSB)

k7 k6 k5 k4 k7 k6 k5 k4

n + 10

5Ah

k3 k2 k1 k0 k3 k2 k1 k0

n + 11

A5h

Product data sheet

COMPANY PUBLIC

Rev. 3.7 — 27 February 2014

073937 19 of 127

NXP Semiconductors

CLRC632

Standard multi-protocol reader solution

9.3 FIFO buffer

An 8  64 bit FIFO buffer is used in the CLRC632 to act as a parallel-to-parallel converter.

It buffers both the input and output data streams between the microprocessor and the

internal circuitry of the CLRC632. This makes it possible to manage data streams up to 64

bytes long without needing to take timing constraints into account.

9.3.1 Accessing the FIFO buffer

9.3.1.1 Access rules

The FIFO buffer input and output data bus is connected to the FIFOData register. Writing

to this register stores one byte in the FIFO buffer and increments the FIFO buffer write

pointer. Reading from this register shows the FIFO buffer contents stored at the FIFO

buffer read pointer and increments the FIFO buffer read pointer. The distance between the

write and read pointer can be obtained by reading the FIFOLength register.

When the microprocessor starts a command, the CLRC632 can still access the FIFO

buffer while the command is running. Only one FIFO buffer has been implemented which

is used for input and output. Therefore, the microprocessor must ensure that there are no

inadvertent FIFO buffer accesses. Table 18

gives an overview of FIFO buffer access

during command processing.

9.3.2 Controlling the FIFO buffer

In addition to writing to and reading from the FIFO buffer, the FIFO buffer pointers can be

reset using the FlushFIFO bit. This changes the FIFOLength[6:0] value to zero, bit

FIFOOvfl is cleared and the stored bytes are no longer accessible. This enables the FIFO

buffer to be written with another 64 bytes of data.

Table 18. FIFO buffer access

Active

command

FIFO buffer Remark

p Write p Read

StartUp - -

Idle - -

Transmit yes -

Receive - yes

Transceive yes yes the microprocessor has to know the state of the

command (transmitting or receiving)

WriteE2 yes -

ReadE2 yes yes the microprocessor has to prepare the arguments,

afterwards only reading is allowed

LoadKeyE2 yes -

LoadKey yes -

Authent1 yes -

Authent2 - -

LoadConfig yes -

CalcCRC yes -

Product data sheet

COMPANY PUBLIC

Rev. 3.7 — 27 February 2014

073937 20 of 127

NXP Semiconductors

CLRC632

Standard multi-protocol reader solution

9.3.3 FIFO buffer status information

The microprocessor can get the following FIFO buffer status data:

• the number of bytes stored in the FIFO buffer: bits FIFOLength[6:0]

• the FIFO buffer full warning: bit HiAlert

• the FIFO buffer empty warning: bit LoAlert

• the FIFO buffer overflow warning: bit FIFOOvfl.

Remark: Setting the FlushFIFO bit clears the FIFOOvfl bit.

The CLRC632 can generate an interrupt signal when:

• bit LoAlertIRq is set to logic 1 and bit LoAlert = logic 1, pin IRQ is activated.

• bit HiAlertIRq is set to logic 1 and bit HiAlert = logic 1, pin IRQ activated.

The HiAlert flag bit is set to logic 1 only when the WaterLevel[5:0] bits or less can be

stored in the FIFO buffer. The trigger is generated by Equation 1

(1)

The LoAlert flag bit is set to logic 1 when the FIFOLevel register’s WaterLevel[5:0] bits or

less are stored in the FIFO buffer. The trigger is generated by Equation 2

(2)

9.3.4 FIFO buffer registers and flags

Table 18 shows the related FIFO buffer flags in alphabetic order.

9.4 Interrupt request system

The CLRC632 indicates interrupt events by setting the PrimaryStatus register bit IRq (see

Section 10.5.1.4 “

PrimaryStatus register” on page 51) and activating pin IRQ. The signal

on pin IRQ can be used to interrupt the microprocessor using its interrupt handling

capabilities ensuring efficient microprocessor software.

HiAlert 64 FIFOLength–WaterLevel=

LoAlert FIFOLength WaterLevel=

Table 19. Associated FIFO buffer registers and flags

Flags Register name Bit Register address

FIFOLength[6:0] FIFOLength 6 to 0 04h

FIFOOvfl ErrorFlag 4 0Ah

FlushFIFO Control 0 09h

HiAlert PrimaryStatus 1 03h

HiAlertIEn InterruptEn 1 06h

HiAlertIRq InterruptRq 1 07h

LoAlert PrimaryStatus 0 03h

LoAlertIEn InterruptEn 0 06h

LoAlertIRq InterruptRq 0 07h

WaterLevel[5:0] FIFOLevel 5 to 0 29h

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