10B.2.5 THS Control Register (THSCR) ............................................................................................................ 10B-9
10B.2.6 THS Status Register (THSSR) ............................................................................................................. 10B-10
10B.2.7 Interrupt Control Register (INTCTLR) ................................................................................................ 10B-11
10B.2.8 CIVM Status Register (CIVM_SR)...................................................................................................... 10B-12
10B.3 Operation ........................................................................................................................................................ 10B-13
10B.3.1 Initial Sequence of Thermal Sensor ..................................................................................................... 10B-13
10B.3.2 Initial Sequence of Chip Internal Voltage Monitor (R-Car V3M Only) .............................................. 10B-13
10B.3.3 Temperature Measurement Using Register (When CPCTL = 0) ......................................................... 10B-14
10B.3.4 Temperature Measurement Using Register (When CPCTL = 1) ......................................................... 10B-14
10B.3.5 Chip Internal Voltage Monitor Using Registers (R-Car V3M Only) ................................................... 10B-14
10B.3.6 Interrupt ................................................................................................................................................ 10B-15
10B.3.7 Standby Mode ...................................................................................................................................... 10B-15
10B.3.8 Software Reset ..................................................................................................................................... 10B-16
10B.3.9 Power Voltage ...................................................................................................................................... 10B-17
10B.3.10 Input/output Clock ................................................................................................................................ 10B-17
10B.3.11 The Temperature Measurement Using External Pins (R-Car V3M and R-Car E3) ............................. 10B-17
10B.4 Usage Note ...................................................................................................................................................... 10B-19
11. Reset (RST) .............................................................................................................................. 11-1
11.1 Overview .............................................................................................................................................................. 11-1
11.1.1 Features ..................................................................................................................................................... 11-1
11.1.2 Block Diagram .......................................................................................................................................... 11-2
11.1.3 External Pins ............................................................................................................................................. 11-7
11.1.4 Register Configuration .............................................................................................................................. 11-8
11.1.5 Connected module ................................................................................................................................... 11-15
11.2 Register Description ........................................................................................................................................... 11-16
11.2.1 Mode Monitor Register (MODEMR) ...................................................................................................... 11-16
11.2.2 Cortex-A57 Reset Control Register (CA57RESCNT) ............................................................................ 11-20
11.2.3 Cortex-A53 Reset Control Register (CA53RESCNT) ............................................................................ 11-22
11.2.4 Reserved .................................................................................................................................................. 11-23
11.2.5 Watchdog Timer Reset Control Register (WDTRSTCR) ....................................................................... 11-24
11.2.6 PRESETOUT# Control Register (RSTOUTCR) .................................................................................... 11-26
11.2.7 Reserved .................................................................................................................................................. 11-26
11.2.8 SYS Boot Address Register (SBAR) ...................................................................................................... 11-27
11.2.9 SYS Boot Address Register2 (SBAR2) .................................................................................................. 11-27
11.2.10 Reserved .................................................................................................................................................. 11-28
11.2.11 Cortex-R7 Boot Address Register (CR7BAR) ........................................................................................ 11-29
11.2.12 Cortex-R7 Boot Address Register2 (CR7BAR2) .................................................................................... 11-31
11.2.13 ICUMX Boot Address Register (ICUMXBAR) ..................................................................................... 11-32
11.2.14 Cortex-A53 Boot Address Register (CA53BAR) ................................................................................... 11-33
11.2.15 Cortex-A53 Boot Address Register2 (CA53BAR2)................................................................................ 11-35
11.2.16 Cortex-A57 Boot Address Register (CA57BAR) ................................................................................... 11-36
11.2.17 Cortex-A57 Boot Address Register2 (CA57BAR2)................................................................................ 11-38
11.2.18 Cortex-A57 CPUn (n=0 to 3[H3], n=0 and 1[M3-W, M3-N]) Boot Address Register for
64-bit mode H (CA57CPUnBARH) ........................................................................................................ 11-39
11.2.19 Cortex-A57 CPUn (n=0 to 3[H3], n=0 and 1[M3-W, M3-N]) Boot Address Register for
64-bit mode L (CA57CPUnBARL)......................................................................................................... 11-40
11.2.20 Cortex-A53 CPUn (n=0 to 3[R-Car H3, R-Car M3-W], n=0 and 1[R-Car V3 V3M], n=0[R-Car D3])
Boot Address Register for 64-bit mode H (CA53CPUnBARH) ............................................................. 11-42
11.2.21 Cortex-A53 CPUn (n=0 to 3[R-Car H3, R-Car M3-W], n=0 and 1[R-Car V3M], n=0[R-Car D3])
Boot Address Register for 64-bit mode L (CA53CPUnBARL) .............................................................. 11-43
11.2.22 APB bus Safety Check Register (APBSFTYCHKR) .............................................................................. 11-46
11.2.23 Standby Flag Register n (STBCHRn) (n=0 to 7) .................................................................................... 11-47
11.2.24 Soft Power On Reset Control Register (SRESCR) ................................................................................. 11-48