瑞萨电子R-Car Gen3硬件用户手册

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“RCarGen3HWUsersManual.pdf是瑞萨电子公司(Renesas Electronics Corp.)推出的R-Car系列第三世代用户手册，主要针对汽车信息终端应用的系统级芯片(SoC)。该手册包含了R-Car H3、R-Car M3-W、R-Car V3M、R-Car V3H、R-Car D3、R-Car M3-N以及R-Car E3等产品的硬件信息，旨在帮助开发者进行BSP(板级支持包)的开发。” 在本手册中，瑞萨电子详细介绍了R-Car系列的不同型号及其具体规格。例如： 1. R-Car H3基于R8A77951芯片，是第一版样品。 2. R-Car M3-W采用R8A77960芯片，处于工程样本(ES)阶段。 3. R-Car V3M是基于R8A77970的，同样是第一版样品。 4. R-Car V3H搭载R8A77980芯片，同样为第一版样品。 5. R-Car D3使用R8A77995芯片，同样是第一版样品。 6. R-Car M3-N配备了R8A77965芯片，同样是第一版样品。 7. R-Car E3则采用了R8A77990芯片，同样为第一版样品。手册内容涵盖了这些SoC的硬件特性，如处理器核心、内存接口、外设接口、电源管理、时钟系统等关键信息。特别指出，对于R-Car M3-W，手册中的内容已经达到了工程样本规范，但DBSC4 DDR3/DDR3L部分尚未完成全面测试。这个硬件手册版本0.80标志着R-Car M3-W的设计完成，而其他产品版本则是0.56。尽管如此，手册提供了关于所有这些产品的基本硬件信息，对开发者理解和配置这些SoC至关重要。手册还提醒用户，所有信息在发布时都是最新的，但可能会随时间更新，建议定期查阅瑞萨电子公司的最新发布信息。 Renesas的R-Car Gen3 HW用户手册是开发汽车电子系统的宝贵资源，提供了R-Car系列SoC的详细硬件指南，包括各个型号的特性和配置，对进行BSP开发的工程师来说极具价值。

9.2.2 Power Control Registers for SCU of Cortex-A53, IMP-X5, SCU of Cortex-A57, Cortex-R7, A3VP,

A3VIP, A3VIP1, V3IP2 and A3VC. ......................................................................................................... 9-75

9.2.2.1 Power Status Register n (PWRSRn) (n = 3/4/5/7/8/9/12/13/14) .................................................. 9-76

9.2.2.2 Power Shutoff Control Register n (PWROFFCRn) (n = 3/4/5/7/8/9/12/13/14) ........................... 9-77

9.2.2.3 Power Shutoff Status Register n (PWROFFSRn) (n = 3/4/5/7/8/9/12/13/14) .............................. 9-78

9.2.2.4 Power Resume Control Register n (PWRONCRn) (n = 3/4/5/7/8/9/12/13/14) ............................ 9-79

9.2.2.5 Power Resume Status Register n (PWRONSRn) (n = 3/4/5/7/8/9/12/13/14) .............................. 9-80

9.2.2.6 Power Shutoff/Resume Error Register n (PWRERn) (n = 3/4/5/7/8/9/12/13/14) ........................ 9-81

9.2.2.7 Power Pseudo Shutoff Register n (PWRPSEUn) (n = 3/4/5/7/8/9) .............................................. 9-82

9.2.2.8 Power Isolation Error Detection Register n (PWRISOERn) (n = 3/4/5/7/8/9/12/13/14) ............. 9-83

9.2.3 Power Control Registers for 3D Graphics Engine ..................................................................................... 9-84

9.2.3.1 Power Status Register n (PWRSRn) (n = 2) ................................................................................. 9-85

9.2.3.2 Power Shutoff Control Register n (PWROFFCRn) (n = 2).......................................................... 9-86

9.2.3.3 Power Shutoff Status Register n (PWROFFSRn) (n = 2) ............................................................ 9-87

9.2.3.4 Power Resume Control Register n (PWRONCRn) (n = 2) .......................................................... 9-88

9.2.3.5 Power Resume Status Register n (PWRONSRn) (n = 2) ............................................................. 9-89

9.2.3.6 Power Shutoff/Resume Error Register n (PWRERn) (n = 2) ....................................................... 9-90

9.2.3.7 Power Pseudo Shutoff Register n (PWRPSEUn) (n = 2) ............................................................. 9-91

9.2.3.8 Power Isolation Error Detection Register n (PWRISOERn) (n = 2) ............................................ 9-92

9.2.4 Power Control Registers for A2VC. .......................................................................................................... 9-93

9.2.4.1 Power Status Register n (PWRSRn) (n = 10) ............................................................................... 9-93

9.2.4.2 Power Shutoff Control Register n (PWROFFCRn) (n = 10) ........................................................ 9-94

9.2.4.3 Power Shutoff Status Register n (PWROFFSRn) (n = 10) .......................................................... 9-95

9.2.4.4 Power Resume Control Register n (PWRONCRn) (n = 10) ........................................................ 9-96

9.2.4.5 Power Resume Status Register n (PWRONSRn) (n = 10) ........................................................... 9-97

9.2.4.6 Power Shutoff/Resume Error Register n (PWRERn) (n = 10) ..................................................... 9-98

9.2.4.7 Power Pseudo Shutoff Register n (PWRPSEUn) (n = 10) ........................................................... 9-98

9.2.4.8 Power Isolation Error Detection Register n (PWRISOERn) (n = 10) .......................................... 9-99

9.2.5 Power Control Registers for A2IR/A2SC/A2PD/A2CN. ........................................................................ 9-100

9.2.5.1 Power Status Register n (PWRSRn) (n = 11) ............................................................................. 9-100

9.2.5.2 Power Shutoff Control Register n (PWROFFCRn) (n = 11) ...................................................... 9-102

9.2.5.3 Power Shutoff Status Register n (PWROFFSRn) (n = 11) ........................................................ 9-104

9.2.5.4 Power Resume Control Register n (PWRONCRn) (n = 11) ...................................................... 9-106

9.2.5.5 Power Resume Status Register n (PWRONSRn) (n = 11) ......................................................... 9-108

9.2.5.6 Power Shutoff/Resume Error Register n (PWRERn) (n = 11) ................................................... 9-110

9.2.5.7 Power Pseudo Shutoff Register n (PWRPSEUn) (n = 11) ......................................................... 9-112

9.2.5.8 Power Isolation Error Detection Register n (PWRISOERn) (n = 11) ........................................ 9-114

9.2.5.9 Power Isolation Error Detection Register n (PWRISOERLn) (n = 11) ...................................... 9-114

9.2.5.10 Power Isolation Error Detection Register n (PWRISOERHn) (n = 11) ..................................... 9-115

9.3 Operation ........................................................................................................................................................... 9-116

9.3.1 Power domain structure ........................................................................................................................... 9-116

9.3.2 Initial state of power domains ................................................................................................................. 9-121

9.3.3 Power Control of Arm CPUs ................................................................................................................... 9-123

9.3.4 Power Control of non Arm CPU modules ............................................................................................... 9-124

9.4 Usage Notes ....................................................................................................................................................... 9-125

9A. Adaptive Voltage Scaling (AVS) ........................................................................................... 9A-1

9A.1 Overview ............................................................................................................................................................. 9A-1

9A.1.1 Features .................................................................................................................................................... 9A-1

9A.1.2 Block Diagram ......................................................................................................................................... 9A-2

9A.1.3 External Pins ............................................................................................................................................ 9A-3

9A.1.4 Register Configuration. ............................................................................................................................ 9A-4

9A.1.5 Connected Module ................................................................................................................................... 9A-4

9A.2 Register Description ............................................................................................................................................ 9A-5

9A.2.1 Adaptive Dynamic Voltage ADJust Parameter (ADVADJP) .................................................................. 9A-5

9A.3 Operation ............................................................................................................................................................ 9A-6

9A.3.1 AVS code ................................................................................................................................................. 9A-6

10A. Thermal Sensor/Chip Internal Voltage Monitor (THS/CIVM) ......................................... 10A-1

10A.1 Overview ........................................................................................................................................................... 10A-1

10A.1.1 Features .................................................................................................................................................. 10A-1

10A.1.2 Block Diagram ....................................................................................................................................... 10A-1

10A.1.3 External Pins .......................................................................................................................................... 10A-3

10A.1.4 Register Configuration ........................................................................................................................... 10A-3

10A.1.5 Connected Module ................................................................................................................................. 10A-4

10A.2 Register Description .......................................................................................................................................... 10A-5

10A.2.1 Interrupt Status Register (IRQSTR) ....................................................................................................... 10A-6

10A.2.2 Interrupt Mask Register (IRQMSK) ....................................................................................................... 10A-7

10A.2.3 Threshold Edge/Level Register (IRQCTL) ............................................................................................ 10A-8

10A.2.4 Interrupt Enable Register (IRQEN) ........................................................................................................ 10A-9

10A.2.5 Interrupt Temperature 1 Register (IRQTEMP1) .................................................................................. 10A-10

10A.2.6 Interrupt Temperature 2 Register (IRQTEMP2) .................................................................................. 10A-10

10A.2.7 Interrupt Temperature 3 Register (IRQTEMP3) .................................................................................. 10A-11

10A.2.8 Control Register (THCTR) ................................................................................................................... 10A-12

10A.2.9 Status Register (THSTR)...................................................................................................................... 10A-13

10A.2.10 Temperature Register (TEMP) ............................................................................................................. 10A-14

10A.2.11 Voltage Register (VOLT) ..................................................................................................................... 10A-14

10A.2.12 THCODE Parameter1 Register (THCODE1) ....................................................................................... 10A-15

10A.2.13 THCODE Parameter2 Register (THCODE2) ....................................................................................... 10A-15

10A.2.14 THCODE Parameter3 Register (THCODE3) ....................................................................................... 10A-16

10A.2.15 PTAT Parameter1 Register (PTAT1) ................................................................................................... 10A-16

10A.2.16 PTAT Parameter2 Register (PTAT2) ................................................................................................... 10A-17

10A.2.17 PTAT Parameter3 Register (PTAT3) ................................................................................................... 10A-17

10A.2.18 Software Correction Parameter Register (THSCP) .............................................................................. 10A-18

10A.3 Operation ........................................................................................................................................................ 10A-19

10A.3.1 The Initial Sequence of Thermal Sensor/Chip Internal Voltage Monitor ............................................. 10A-19

10A.3.1.1

Setting of Normal Mode .......................................................................................................... 10A-19

10A.3.1.2 Normal Mode .......................................................................................................................... 10A-20

10A.3.2 Interrupt ................................................................................................................................................ 10A-21

10A.3.3 Standby Mode ...................................................................................................................................... 10A-22

10A.3.4 Software Reset ..................................................................................................................................... 10A-23

10A.3.5 Power Voltage ...................................................................................................................................... 10A-25

10A.3.6 Input/output Clock ................................................................................................................................ 10A-25

10A.4 Usage Note ...................................................................................................................................................... 10A-26

10B. Thermal Sensor/Chip Internal Voltage Monitor (THS/CIVM) .......................................... 10B-1

10B.1 Overview ........................................................................................................................................................... 10B-1

10B.1.1 Features .................................................................................................................................................. 10B-1

10B.1.2 Block Diagram ....................................................................................................................................... 10B-1

10B.1.3 External Pins .......................................................................................................................................... 10B-3

10B.1.4 Register Configuration ........................................................................................................................... 10B-3

10B.1.5 Connected Module ................................................................................................................................. 10B-4

10B.2 Register Description .......................................................................................................................................... 10B-5

10B.2.1 Interrupt Status Register (STR) .............................................................................................................. 10B-5

10B.2.2 Interrupt Enable Register (ENR) ............................................................................................................ 10B-6

10B.2.3 Interrupt Mask Register (INT_MASK) .................................................................................................. 10B-7

10B.2.4 Positive/Negative Logic Select Register (POSNEG) ............................................................................. 10B-8

10B.2.5 THS Control Register (THSCR) ............................................................................................................ 10B-9

10B.2.6 THS Status Register (THSSR) ............................................................................................................. 10B-10

10B.2.7 Interrupt Control Register (INTCTLR) ................................................................................................ 10B-11

10B.2.8 CIVM Status Register (CIVM_SR)...................................................................................................... 10B-12

10B.3 Operation ........................................................................................................................................................ 10B-13

10B.3.1 Initial Sequence of Thermal Sensor ..................................................................................................... 10B-13

10B.3.2 Initial Sequence of Chip Internal Voltage Monitor (R-Car V3M Only) .............................................. 10B-13

10B.3.3 Temperature Measurement Using Register (When CPCTL = 0) ......................................................... 10B-14

10B.3.4 Temperature Measurement Using Register (When CPCTL = 1) ......................................................... 10B-14

10B.3.5 Chip Internal Voltage Monitor Using Registers (R-Car V3M Only) ................................................... 10B-14

10B.3.6 Interrupt ................................................................................................................................................ 10B-15

10B.3.7 Standby Mode ...................................................................................................................................... 10B-15

10B.3.8 Software Reset ..................................................................................................................................... 10B-16

10B.3.9 Power Voltage ...................................................................................................................................... 10B-17

10B.3.10 Input/output Clock ................................................................................................................................ 10B-17

10B.3.11 The Temperature Measurement Using External Pins (R-Car V3M and R-Car E3) ............................. 10B-17

10B.4 Usage Note ...................................................................................................................................................... 10B-19

11. Reset (RST) .............................................................................................................................. 11-1

11.1 Overview .............................................................................................................................................................. 11-1

11.1.1 Features ..................................................................................................................................................... 11-1

11.1.2 Block Diagram .......................................................................................................................................... 11-2

11.1.3 External Pins ............................................................................................................................................. 11-7

11.1.4 Register Configuration .............................................................................................................................. 11-8

11.1.5 Connected module ................................................................................................................................... 11-15

11.2 Register Description ........................................................................................................................................... 11-16

11.2.1 Mode Monitor Register (MODEMR) ...................................................................................................... 11-16

11.2.2 Cortex-A57 Reset Control Register (CA57RESCNT) ............................................................................ 11-20

11.2.3 Cortex-A53 Reset Control Register (CA53RESCNT) ............................................................................ 11-22

11.2.4 Reserved .................................................................................................................................................. 11-23

11.2.5 Watchdog Timer Reset Control Register (WDTRSTCR) ....................................................................... 11-24

11.2.6 PRESETOUT# Control Register (RSTOUTCR) .................................................................................... 11-26

11.2.7 Reserved .................................................................................................................................................. 11-26

11.2.8 SYS Boot Address Register (SBAR) ...................................................................................................... 11-27

11.2.9 SYS Boot Address Register2 (SBAR2) .................................................................................................. 11-27

11.2.10 Reserved .................................................................................................................................................. 11-28

11.2.11 Cortex-R7 Boot Address Register (CR7BAR) ........................................................................................ 11-29

11.2.12 Cortex-R7 Boot Address Register2 (CR7BAR2) .................................................................................... 11-31

11.2.13 ICUMX Boot Address Register (ICUMXBAR) ..................................................................................... 11-32

11.2.14 Cortex-A53 Boot Address Register (CA53BAR) ................................................................................... 11-33

11.2.15 Cortex-A53 Boot Address Register2 (CA53BAR2)................................................................................ 11-35

11.2.16 Cortex-A57 Boot Address Register (CA57BAR) ................................................................................... 11-36

11.2.17 Cortex-A57 Boot Address Register2 (CA57BAR2)................................................................................ 11-38

11.2.18 Cortex-A57 CPUn (n=0 to 3[H3], n=0 and 1[M3-W, M3-N]) Boot Address Register for

64-bit mode H (CA57CPUnBARH) ........................................................................................................ 11-39

11.2.19 Cortex-A57 CPUn (n=0 to 3[H3], n=0 and 1[M3-W, M3-N]) Boot Address Register for

64-bit mode L (CA57CPUnBARL)......................................................................................................... 11-40

11.2.20 Cortex-A53 CPUn (n=0 to 3[R-Car H3, R-Car M3-W], n=0 and 1[R-Car V3 V3M], n=0[R-Car D3])

Boot Address Register for 64-bit mode H (CA53CPUnBARH) ............................................................. 11-42

11.2.21 Cortex-A53 CPUn (n=0 to 3[R-Car H3, R-Car M3-W], n=0 and 1[R-Car V3M], n=0[R-Car D3])

Boot Address Register for 64-bit mode L (CA53CPUnBARL) .............................................................. 11-43

11.2.22 APB bus Safety Check Register (APBSFTYCHKR) .............................................................................. 11-46

11.2.23 Standby Flag Register n (STBCHRn) (n=0 to 7) .................................................................................... 11-47

11.2.24 Soft Power On Reset Control Register (SRESCR) ................................................................................. 11-48

11.2.25 RT Reset Flag Register (RRSTFR) ......................................................................................................... 11-49

11.2.26 SYS Reset Flag Register (SRSTFR) ....................................................................................................... 11-50

11.2.27 Secure Protect Control/Status Register (SCPTCSR) ............................................................................... 11-51

11.2.28 Secure Error Master ID Register (SCERMIDR) ..................................................................................... 11-53

11.2.29 Secure Error Address Register (SCERADR) .......................................................................................... 11-55

11.2.30 Safety Protect Control/Status Register (SAPTCSR) ............................................................................... 11-57

11.2.31 Safety Error Master ID Register (SAERMIDR) ...................................................................................... 11-58

11.2.32 Safety Error Address Register (SAERADR) ........................................................................................... 11-58

11.2.33 Cortex-R7 Control Register (CR7CR) .................................................................................................... 11-59

11.3 Operation ........................................................................................................................................................... 11-60

11.3.1 Power-On Reset by PRESET# Pin .......................................................................................................... 11-60

11.3.2 WDT reset ............................................................................................................................................... 11-62

12. Interrupt Controller (INTC) ..................................................................................................... 12-1

12.1 Overview .............................................................................................................................................................. 12-1

12.1.1 Features ..................................................................................................................................................... 12-1

12.1.2 Block Diagram .......................................................................................................................................... 12-1

12.1.3 External Pins ............................................................................................................................................. 12-2

12.1.4 Register Configuration .............................................................................................................................. 12-3

12.1.5 Connected Module .................................................................................................................................... 12-3

12.2 Register Description ............................................................................................................................................. 12-4

12.2.1 INTC-RT Routing Control Register (INTCRTRCR) ................................................................................ 12-4

12.2.2 INTC-Monitor Security Error Status Register (IMNTRSESR) ................................................................. 12-7

12.2.3 INTC-Monitor Error Slave Address Register (IMNTRESADDR) ........................................................... 12-8

12.2.4 INTC-Monitor Counter Control Register (IMNTRCCR) .......................................................................... 12-9

12.2.5 INTC-Monitor Control Register n (IMNTRCRn) ................................................................................... 12-10

12.2.6 INTC-Monitor Status Register n (IMNTRSRn) ...................................................................................... 12-10

12.2.7 INTC-Monitor Runtime Test Register n (IMNTRRTRn) ....................................................................... 12-11

12.3 Operation ........................................................................................................................................................... 12-12

12.3.1 Connecting INTC-RT’s port to AP cluster’s core ................................................................................... 12-12

12A. Interrupt Controller (INTC-AP) ......................................................................................... 12A-1

12A.1 Overview ........................................................................................................................................................... 12A-1

12A.1.1 Features .................................................................................................................................................. 12A-1

12A.1.2 Block Diagram ....................................................................................................................................... 12A-1

12A.1.3 External Pins .......................................................................................................................................... 12A-1

12A.1.4 Register Configuration ........................................................................................................................... 12A-1

12A.1.5 Connected Module ................................................................................................................................. 12A-2

12A.2 Register Description .......................................................................................................................................... 12A-3

12A.3 Operation .......................................................................................................................................................... 12A-4

12A.3.1 INTC-AP Register Configuration and Function Description ................................................................. 12A-4

12A.3.2 Interrupts Mapping ................................................................................................................................. 12A-5

12B. Interrupt Controller (INTC-RT) ......................................................................................... 12B-1

12B.1 Overview ........................................................................................................................................................... 12B-1

12B.1.1 Features .................................................................................................................................................. 12B-1

12B.1.2 Block Diagram ....................................................................................................................................... 12B-1

12B.1.3 External Pins .......................................................................................................................................... 12B-1

12B.1.4 Register Configuration ........................................................................................................................... 12B-1

12B.1.5 Connected Module ................................................................................................................................. 12B-2

12B.2 Register Description .......................................................................................................................................... 12B-2

12B.3 Operation .......................................................................................................................................................... 12B-3

12B.3.1 INTC-RT Register Configuration and Function Description ................................................................. 12B-3

12B.3.2 Interrupts Mapping ................................................................................................................................. 12B-4

13. Interrupt Controller (INTC-EX) .............................................................................................. 13-1

13.1 Overview .............................................................................................................................................................. 13-1

13.1.1 Features ..................................................................................................................................................... 13-1

13.1.2 Block Diagram .......................................................................................................................................... 13-1

13.1.3 External Pins ............................................................................................................................................. 13-2

13.1.4 Register Configuration .............................................................................................................................. 13-2

13.1.5 Connected Module .................................................................................................................................... 13-5

13.2 Register Description ............................................................................................................................................. 13-6

13.2.1 Interrupt Request Status Register0 (INTREQ_STS0) ............................................................................... 13-6

13.2.2 Interrupt Enable Status Register0 (INTEN_STS0) ................................................................................... 13-7

13.2.3 Interrupt Enable Set Register0 (INTEN_SET0) ........................................................................................ 13-8

13.2.4 IRQn Detect Status Register (DETECT_STATUS) .................................................................................. 13-9

13.2.5 IRQn Signal Level Monitor Register (MONITOR) ................................................................................ 13-10

13.2.6 IRQn High Level Detect Status Register (HLVL_STS) .......................................................................... 13-11

13.2.7 IRQn Low Level Detect Status Register (LLVL_STS) ........................................................................... 13-12

13.2.8 IRQn Sync Rising Edge Detect Status Register (S_R_EDGE_STS) ...................................................... 13-13

13.2.9 IRQn Sync Falling Edge Detect Status Register (S_F_EDGE_STS) ...................................................... 13-14

13.2.10 IRQn Async Rising Edge Detect Status Register (A_R_EDGE_STS) ................................................... 13-15

13.2.11 IRQn Async Falling Edge Detect Status Register (A_F_EDGE_STS) ................................................... 13-16

13.2.12 IRQn Chattering Reduction Status Register (CHTEN_STS) .................................................................. 13-17

13.2.13 IRQn Configuration Register (CONFIG_n) ............................................................................................ 13-18

13.2.14 NMI Request Status Register 0 (NMIREQ_STS0) ................................................................................. 13-20

13.2.15 NMI Enable Status Register 0 (NMIEN_STS0) ...................................................................................... 13-22

13.2.16 NMI Enable Set Register 0 (NMIEN_SET0) .......................................................................................... 13-25

13.2.17 NMI Detect Status Register (DETECT_STATUS_NMI) ....................................................................... 13-27

13.2.18 NMI Signal Level Monitor Register (MONITOR_NMI) ........................................................................ 13-31

13.2.19 NMI High Level Detect Status Register (HLVL_STS_NMI) ................................................................. 13-34

13.2.20 NMI Low Level Detect Status Register (LLVL_STS_NMI) .................................................................. 13-37

13.2.21 NMI Sync Rising Edge Detect Status Register (S_R_EDGE_STS_NMI) .............................................. 13-40

13.2.22 NMI Sync Falling Edge Detect Status Register (S_F_EDGE_STS_NMI) ............................................. 13-43

13.2.23 NMI Async Rising Edge Detect Status Register (A_R_EDGE_STS_NMI) ........................................... 13-46

13.2.24 NMI Async Falling Edge Detect Status Register (A_F_EDGE_STS_NMI) .......................................... 13-49

13.2.25 NMI Chattering Reduction Status Register (CHTEN_STS_NMI) .......................................................... 13-52

13.2.26 NMI Debounce Setting Register (DEB_SET_NMI) ............................................................................... 13-53

13.2.27 NMI Configuration n Register (CONFIGn_NMI) .................................................................................. 13-54

13.2.28 NMI Mask Lock Set Register (NMI_LCK) ............................................................................................ 13-55

13.2.29 NMI Lock Code Register (NMI_LCKCODE) ........................................................................................ 13-55

13.2.30 NMI Debug Control Enable Register (NMI_DBG) ................................................................................ 13-56

13.2.31 NMI Debug Code Register (NMI_DBGCODE) ..................................................................................... 13-56

13.3 Operation ........................................................................................................................................................... 13-57

13.3.1 NMI Mask Lock Feature ......................................................................................................................... 13-57

13.3.2 Procedure of NMI Mask Lock ................................................................................................................. 13-57

14. Multifunctional Interface (MFIS) ............................................................................................ 14-1

14.1 Overview .............................................................................................................................................................. 14-1

14.1.1 Features ..................................................................................................................................................... 14-1

14.1.2 Block Diagram .......................................................................................................................................... 14-1

14.1.3 External Pins ............................................................................................................................................. 14-1

14.1.4 Register Configuration .............................................................................................................................. 14-2

14.1.5 Connected Module .................................................................................................................................. 14-16

14.2 Register Description ........................................................................................................................................... 14-17

14.2.1 MFIS Lock Registers n (MFISLCKRn) .................................................................................................. 14-17

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