STM32系列工程师入门指南

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"这篇资源是《工程师对STM32系列的入门指南》，主要介绍基于ARM Cortex-M3的STM32微控制器，由Hitex（UK）Ltd出版，内容包括STM32的概述、特性、软件开发以及性能和访问线等方面。书中包含丰富的原理图，并得到了STMicroelectronics的协助。" STM32系列是微控制器领域的一个重要组成部分，尤其在嵌入式系统设计中广泛应用。STM32是由意法半导体（STMicroelectronics）推出的基于ARM Cortex-M3内核的32位微控制器家族。Cortex-M3是ARM公司设计的一种高效能、低功耗的处理器核心，特别适合于实时控制和嵌入式应用。 1. Cortex内核简介： Cortex-M3是ARM的微控制器级CPU核心，它以精简指令集(RISC)为基础，强调了代码效率和处理速度。Cortex-M3具有硬件除法器、嵌套向量中断控制器(NVIC)以及单周期乘法和硬件浮点运算单元（取决于具体型号），在保持低功耗的同时提供了强大的处理能力。 2. STM32的特性： - **复杂性**：STM32家族提供了广泛的选择，包括不同的内存大小、外设接口和性能等级，满足各种项目需求。 - **安全性**：针对安全关键应用，STM32提供安全功能，如独立的看门狗、安全启动和加密硬件加速器，确保数据和系统的安全性。 - **安全性**：STM32还考虑了信息安全，支持安全启动、加密和认证机制，防止未经授权的访问和篡改。 - **软件开发**：为了简化软件开发，STM32支持多种开发工具和RTOS(实时操作系统)，如Keil MDK、IAR EWARM等，以及HAL和LL库，使开发者可以高效地编写代码。 - **STM32性能线和访问线**：性能线产品专注于高性能，而访问线则更注重成本效益和易用性，两者在内存、时钟速度和外设集成方面有所区别，为不同级别的应用提供解决方案。 3. STM32的应用： STM32广泛应用于工业自动化、消费电子、物联网(IoT)设备、医疗设备、汽车电子和电源管理等领域。其丰富的外设接口（如USB、CAN、SPI、I2C、ADC、DAC、GPIO等）使得它能够轻松地连接到各种外围设备。 4. 开发工具和支持：为了支持开发者，STMicroelectronics提供了STM32Cube生态系统，包括STM32CubeMX配置工具、STM32CubeIDE集成开发环境、以及STM32Cube固件库。这些工具帮助快速配置和初始化MCU，生成初始代码，并提供了示例项目，加速开发进程。 5. 学习资源：该《工程师对STM32系列的入门指南》是了解STM32的好起点，结合实际的原理图，可以帮助读者深入理解STM32的工作原理和应用。此外，STMicroelectronics的官方网站和社区也提供了大量的文档、示例代码和在线支持，是学习STM32不可或缺的资源。 STM32系列结合了高性能的Cortex-M3内核和丰富的外设，成为嵌入式系统设计中的热门选择。通过深入理解和掌握STM32的特性，开发者可以有效地利用其功能，构建高效、安全且可靠的嵌入式系统。

Chapter 2: Cortex Overview

Consequently all the program activity focuses around the CPU register file. This register file consists of sixteen

32-bit wide registers. Registers R0-R12 are simple registers that can be used to hold program variables. The

Registers R13-R15 have special functions within the Cortex CPU. Register R13 is used as the stack pointer. This

space. This is typically used by an RTOS which can run its ‘system’ code in a protected mode. In the Cortex CPU

the two stacks are called the main stack and the process stack. The next register R14 is called the link register.

This register is used to store the return address when a call is made to a procedure. This allows the Cortex CPU

to make a fast entry and exit to a procedure. If your code calls several levels of subroutines, the compiler will

automatically store R14 on the stack. The final register R15 is the program counter; since this is part of the central

2.3.2.1 XPSR

In addition to the register file there is a separate register called the Program Status Register. This is not part of

the main register file and is only accessible through two dedicated instructions. The xPSR contains a number of

fields that influence the execution of the Cortex CPU.

The xPSR register can also be accessed through three special alias names that allow access to sub-ranges of

bits within the xPSR. The top five bits are the condition code flags and are aliased as the Application Program

Status Register. The first four condition code flags N,Z,C,V ( Negative, Zero, Carry and Overflow) w i ll be set and

cleared depending on the result of a data processing instruction. The Q bit is used by the DPS saturated maths

instructions to indicate that a variable has reached its maximum or minimum value. Like the ARM 32-bit

instruction set, certain Thumb-2 instructions are only executed if the instruction condition code matches the state

of the Application Program Status Register flags. If the instruction condition codes do not match, the instruction

passes through the pipeline as a NOP. This ensures that instructions flow smoothly through the pipeline and

minimises pipeline flushes. In the Cortex CPU, this technique is extended with the Execution Program Status

The Cortex-M3 has a CPU register file of 16 32-bit wide registers. Like the

earlier ARM7/9 CPUs R13 is the stack pointer. R14 is the link register and

R15 is the PC. R13 is a banked register to allow the Cortex-M3 to operate

with two stacks: a process stack and a main stack.

The Program Status Register contains status fields for instruction execution. This register is

aliased into the Application, Execution and Interrupt Status Registers

Chapter 2: Cortex Overview

2.3.3 CPU Operating Modes

While the Cortex processor is designed to be a low gate count, fast and easy to use microcontroller core, it has

been designed to support the use of a real-time operating system. The Cortex processor has two operating

modes: Thread mode and Handler mode. The CPU will run in Thread mode while it is executing in non-interrupt

background mode and will switch to the Handler mode when it is executing exceptions. In addition, the Cortex

CPU can execute code in a privileged or non-privileged mode. In privileged mode, the CPU has access to the full

instruction set. In unprivileged mode certain instructions are disabled (such as the MRS and MSR instructions

which allow access to the xPSR and its aliases). Additionally, access to most registers in the Cortex processor

system control space is also disabled. Stack usage can also be configured. The main stack (R13) can be used by

both Thread and Handler mode. Alternatively, Handler mode can be configured to use the process stack ( R1 3

banked register).

Out of reset the Cortex processor will run in a ‘flat’ configuration. Both Thread and Handler modes execute in

privileged mode, so there are no restrictions on access to any processor resources. Both the Thread and Handler

modes use the main stack. In order to start execution, the Cortex processor simply needs the reset vector and the

start address of the stack to be configured before you can start to execute your application C code. However, if

you are using an RTOS or are developing a safety-critical application, the chip can be used in a mode advanced

configuration where Handler mode (exceptions and the RTOS) runs in privileged mode and uses the main stack

while application code runs in Thread mode with unprivileged access and uses the process stack. This way the

system code and the application code are partitioned and errors in the application code will not cause the RTOS

to crash.

2.3.4 Thumb-2 Instruction Set

The ARM7 and ARM9 CPUs can execute two instruction sets: the ARM 32-bit instruction set and the Thumb 16-

bit instruction set. This allows a developer to optimise his program by selecting the instruction set used for

The Cortex-M3 can be used in a ‘flat’ simple mode. It

is also designed to support real-time operating

systems. It has Handler and Thread modes that can

be configured to use the main and process stacks

and have privileged access to the Cortex system

control registers.

Chapter 2: Cortex Overview

2.3.5 M e m o r y Map

The Cortex-M3 processor is a standardised microcontroller core and as such has a well-defined memory map.

Despite the multiple internal busses this memory map is a linear 4 Gbyte address space.

The first 1Gbyte of memory is split evenly between a code region and a SRAM region. The code space is

optimised to be executed from the I-Code bus. Similarly, the SRAM is reached with the D-code bus. Although

code can be loaded and executed from the SRAM, the instructions would be fetched using the system bus, wh i c h

incurs an extra wait state. It is likely that code would run slower from SRAM than from on-chip FLASH memory

located in the code region. The next 0.5 Gbyte of memory is the on-chip peripheral region. All user peripherals

provided by the microcontroller vendor will be located in this region. The first 1 Mbyte of both the SRAM and

Peripheral regions is bit-addressable using a technique called bit banding. Since all the SRAM and all the user

peripherals on the STM32 are located in these regions all the memory locations of the STM32 can be

manipulated in a word-wide or bitwise fashion. The next 2 Gbyte address space is allocated to external memory-

mapped SRAM and peripherals. The final 0.5 Gbyte is allocated to the internal Cortex processor peripherals and

a region for future vendor specific enhancements to the Cortex processor. All of the Cortex processor registers

are at fixed locations for all Cortex-based microcontrollers. This allows code to be more easily ported between

different STM32 variants and indeed other vendors’ Cortex-based microcontrollers. One processor to learn, one

set of tools to invest in and large amounts of reusable code across a wide range of microcontrollers.

The Cortex-M3 defines a fixed 4

Gb memory map that specifies

regions for code SRAM

peripherals, external memory

and devices and the Cortex

system registers. This memory

map is common to all Cortex-

based devices.

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