MIPS64架构入门：程序员指南

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"MIPS® Architecture For Programmers Volume I-A: Introduction to the MIPS64® Architecture" MIPS（Microprocessor without Interlocked Pipeline Stages）架构是一种精简指令集计算机（RISC）架构，由MIPS Technologies公司开发。MIPS64是MIPS架构的一个版本，设计用于支持64位计算，提供了更强大的处理能力和更大的内存寻址能力。《MIPS® Architecture For Programmers Volume I-A》是MIPS架构系列文档的一部分，主要面向程序员，介绍MIPS64架构的基础知识。这本书可能是由MIPS Technologies在2013年11月20日发布的第五版第四次修订版，编号为MD00083。书中详细阐述了MIPS64处理器的内部工作原理、指令集、编程模型以及如何有效地利用这些知识来编写高效能的软件。 MIPS64架构的核心特点包括： 1. **64位地址空间**：MIPS64扩展了传统的32位地址空间，允许访问超过4GB的内存，适合大数据和高性能计算应用。 2. **增强的指令集**：除了保留原有的32位MIPS指令外，还增加了一系列新的64位指令，以提高运算速度和效率。 3. **浮点处理单元（FPU）**：MIPS64通常包含专为浮点运算设计的硬件，如文档中的“nB1.03,Built with tags: 2BARCHFPU_PSFPU_PS”，这表明支持双精度浮点运算，对科学计算和图形处理非常重要。 4. **多级流水线**：MIPS架构以其高效的流水线设计而闻名，MIPS64可能包含多个阶段的指令执行流水线，以实现更快的指令吞吐量。 5. **向后兼容性**：MIPS64设计时考虑了与早期MIPS架构的兼容性，使得32位代码可以无缝运行在64位平台上。书中可能涵盖的主题有： - **指令格式和操作码**：讲解MIPS64指令的基本结构和编码方式。 - **寄存器系统**：描述MIPS64的通用寄存器、浮点寄存器以及控制和状态寄存器的使用。 - **寻址模式**：介绍各种内存寻址方式，如立即寻址、直接寻址、相对寻址等。 - **程序控制流**：包括跳转、分支和异常处理机制。 - **数据处理**：涵盖算术运算、逻辑运算、比较和移动指令的使用。 - **中断和异常**：解释处理器如何响应中断和异常事件。 - **系统调用**：说明如何使用系统调用来与操作系统交互。 - **编译器支持**：讨论编译器如何生成针对MIPS64架构优化的代码。 - **性能优化**：提供编程技巧，以最大限度地发挥MIPS64处理器的潜能。此文档对于理解和编写针对MIPS64架构的应用程序开发者来说，是一份宝贵的参考资料，它不仅介绍了基本的架构原理，还深入到实际编程的细节，帮助开发者充分利用该平台的特性。同时，由于MIPS Technologies对其内容的版权保护，未经许可的复制、修改或使用可能会引起法律问题。

1.4 For More Information

MIPS® Architecture For Programmers Volume I-A: Introduction to the MIPS64® Architecture, Revision 5.04 16

1.4 For More Information

Various MIPS RISC processor manuals and additional information about MIPS products can be found at the MIPS

URL: http://www.mips.com

For comments or questions on the MIPS64® Architecture or this document, send Email to support@mips.com.

FP32RegistersMode Indicates whether the FPU has 32-bit or 64-bit ﬂoating point registers (FPRs). In MIPS32 Release 1, the FPU

has 32 32-bit FPRs in which 64-bit data types are stored in even-odd pairs of FPRs. In MIPS64, (and option-

ally in MIPS32 Release2 and MIPSr3) the FPU has 32 64-bit FPRs in which 64-bit data types are stored in

any FPR.

In MIPS32 Release 1 implementations, FP32RegistersMode is always a 0. MIPS64 implementations have a

compatibility mode in which the processor references the FPRs as if it were a MIPS32 implementation. In

such a case FP32RegisterMode is computed from the FR bit in the Status register. If this bit is a 0, the pro-

cessor operates as if it had 32 32-bit FPRs. If this bit is a 1, the processor operates with 32 64-bit FPRs.

The value of FP32RegistersMode is computed from the FR bit in the Status register.

InstructionInBranchDe-

laySlot

Indicates whether the instruction at the Program Counter address was executed in the delay slot of a branch

or jump. This condition reﬂects the dynamic state of the instruction, not the static state. That is, the value is

false if a branch or jump occurs to an instruction whose PC immediately follows a branch or jump, but which

is not executed in the delay slot of a branch or jump.

SignalException(excep-

tion, argument)

Causes an exception to be signaled, using the exception parameter as the type of exception and the argument

parameter as an exception-speciﬁc argument). Control does not return from this pseudocode function—the

exception is signaled at the point of the call.

Table 1.1 Symbols Used in Instruction Operation Statements (Continued)

Symbol Meaning

Chapter 2

MIPS® Architecture For Programmers Volume I-A: Introduction to the MIPS64® Architecture, Revision 5.04 17

The MIPS Architecture: An Introduction

2.1 MIPS Instruction Set Overview

2.1.1 Historical Perspective

The MIPS® Instruction Set Architecture (ISA) has evolved over time from the original MIPS I™ ISA, through the

MIPS V™ ISA, to the current MIPS32®, MIPS64® and microMIPS™ Architectures. As the ISA evolved, all exten-

sions have been backward compatible with previous versions of the ISA. In the MIPS III™ level of the ISA, 64-bit

integers and addresses were added to the instruction set. The MIPS IV™ and MIPS V™ levels of the ISA added

improved ﬂoating point operations, as well as a set of instructions intended to improve the efﬁciency of generated

code and of data movement. Because of the strict backward-compatible requirement of the ISA, such changes were

unavailable to 32-bit implementations of the ISA which were, by deﬁnition, MIPS I™ or MIPS II™ implementations.

While the user-mode ISA was always backward compatible, the privileged environment was allowed to change on a

per-implementation basis. As a result, the R3000® privileged environment was different from the R4000® privileged

environment, and subsequent implementations, while similar to the R4000 privileged environment, included subtle

differences. Because the privileged environment was never part of the MIPS ISA, an implementation had the ﬂexibil-

ity to make changes to suit that particular implementation. Unfortunately, this required kernel software changes to

every operating system or kernel environment on which that implementation was intended to run.

Many of the original MIPS implementations were targeted at computer-like applications such as workstations and

servers. In recent years MIPS implementations have had signiﬁcant success in embedded applications. Today, most of

the MIPS parts that are shipped go into some sort of embedded application. Such applications tend to have different

trade-offs than computer-like applications including a focus on cost of implementation, and performance as a func-

tion of cost and power.

The MIPS32 and MIPS64 Architectures are intended to address the need for a high-performance but cost-sensitive

MIPS instruction set. The MIPS32 Architecture is based on the MIPS II ISA, adding selected instructions from MIPS

III, MIPS IV, and MIPS V to improve the efﬁciency of generated code and of data movement. The MIPS64 Architec-

ture is based on the MIPS V ISA and is backward compatible with the MIPS32 Architecture. Both the MIPS32 and

MIPS64 Architectures bring the privileged environment into the Architecture deﬁnition to address the needs of oper-

ating systems and other kernel software. Both also include provision for adding optional components - Modules of the

base architecture, MIPS Application Speciﬁc Extensions (ASEs), User Deﬁned Instructions (UDIs), and custom

coprocessors to address the speciﬁc needs of particular markets.

The MIPS32 and MIPS64 Architectures provide a substantial cost/performance advantage over microprocessor

implementations based on traditional architectures. This advantage is a result of improvements made in several con-

tiguous disciplines: VLSI process technology, CPU organization, system-level architecture, and operating system and

compiler design.

The microMIPS32 and microMIPS64 Architectures deliver the same functionality of MIPS32 and MIPS64 with the

additional beneﬁt of smaller codesizes. The microMIPS architectures are supersets of MIPS32/MIPS64 architectures,

with almost the same sets of 32-bit sized instructions and additional 16-bit instructions to help with codesize. micro-

MIPS is especially compelling for systems in which the cost of memory dominate the entire bill of materials cost.

The MIPS Architecture: An Introduction

19 MIPS® Architecture For Programmers Volume I-A: Introduction to the MIPS64® Architecture, Revision 5.04

• are standardized to prevent fragmentation

• are a superset of the existing architecture

The MIPS Architecture community constantly evaluates suggestions for architectural changes and enhancements

against these criteria. New releases of the architecture, while infrequent, are made at appropriate points, following

these criteria. At present, there are three releases of the MIPS Architecture: Release 1 (the original version of the

MIPS64 Architecture) ; Release 2 which was added in 2002 and Release 3 (called MIPSr3

) which was added in

2010.

2.1.2.1 Release 2 of the MIPS64 Architecture

Enhancements included in Release 2 of the MIPS64 Architecture are:

• Vectored interrupts: This enhancement provides the ability to vector interrupts directly to a handler for that inter-

rupt. Vectored interrupts are an option in Release 2 implementations and the presence of that option is denoted by

the Conﬁg3

VInt

bit.

• Support for an external interrupt controller: This enhancement reconﬁgures the on-core interrupt logic to take

full advantage of an external interrupt controller. This support is an option in Release 2 implementations and the

presence of that option is denoted by the Conﬁg3

EIC

bit.

• Programmable exception vector base: This enhancement allows the base address of the exception vectors to be

moved for exceptions that occur when Status

BEV

is 0. Doing so allows multi-processor systems to have separate

exception vectors for each processor, and allows any system to place the exception vectors in memory that is

appropriate to the system environment. This enhancement is required in a Release 2 implementation.

• Atomic interrupt enable/disable: Two instructions have been added to atomically enable or disable interrupts, and

return the previous value of the Status register. These instructions are required in a Release 2 implementation.

• The ability to disable the Count register for highly power-sensitive applications. This enhancement is required in

a Release 2 implementation.

• GPR shadow registers: This addition provides the addition of GPR shadow registers and the ability to bind these

registers to a vectored interrupt or exception. Shadow registers are an option in Release 2 implementations and

the presence of that option is denoted by a non-zero value in SRSCtl

HSS

. While shadow registers are most useful

when either vectored interrupts or support for an external interrupt controller is also implemented, neither is

required.

• Field, Rotate and Shufﬂe instructions: These instructions add additional capability in processing bit ﬁelds in reg-

isters. These instructions are required in a Release 2 implementation.

• Explicit hazard management: This enhancement provides a set of instructions to explicitly manage hazards, in

place of the cycle-based SSNOP method of dealing with hazards. These instructions are required in a Release 2

implementation.

• Access to a new class of hardware registers and state from an unprivileged mode. This enhancement is required

in a Release 2 implementation.

• Coprocessor 0 Register changes: These changes add or modify CP0 registers to indicate the existence of new and

optional state, provide L2 and L3 cache identiﬁcation, add trigger bits to the Watch registers, and add support for

64-bit performance counter count registers. This enhancement is required in a Release 2 implementation.

2.1 MIPS Instruction Set Overview

MIPS® Architecture For Programmers Volume I-A: Introduction to the MIPS64® Architecture, Revision 5.04 20

• Support for 64-bit coprocessors with 32-bit CPUs: These changes allow a 64-bit coprocessor (including an FPU)

to be attached to a 32-bit CPU. This enhancement is optional in a Release 2 implementation.

• New Support for Virtual and Physical Memory: These changes provide support for a 1KByte page size, and the

ability to support physical addresses larger than 36 bits. Both changes are optional in Release 2 implementations,

and support is denoted by Conﬁg3

(for 1KB page support) and Conﬁg3

LPA

(for larger physical address sup-

port).

2.1.2.2 Releases 2.5+ of the MIPS64 Architecture

Some optional features were added after Revision 2.5:

• TLB pages larger than 256MB are supported. This feature allows large regions to be mapped with fewer TLB

entries, especially within devices with very large memory systems.

• Support for a MMU with more than 64 TLB entries. This feature aids in reducing the frequency of TLB misses.

• Scratch registers within Coprocessor0 for kernel mode software. This feature aids in quicker exception handling

by not requiring the saving of usermode registers onto the stack before kernelmode software uses those registers.

• A MMU conﬁguration which supports both larger set-associative TLBs and variable page-sizes. This feature aids

in reducing the frequency of TLB misses.

• The CDMM memory scheme for the placement of small I/O devices into the physical address space. This

scheme allows for efﬁcient placement of such I/O devices into a small memory region.

• An EIC interrupt mode where the EIC controller supplies a 16-bit interrupt vector. This allows different inter-

rupts to share code.

• The PAUSE instruction to deallocate a (virtual) processor when arbitration for a lock doesn’t succeed. This

allows for lower power consumption as well as lower snoop trafﬁc when multiple (virtual) processors are arbi-

trating for a lock.

• More ﬂavors of memory barriers that are available through stype ﬁeld of the SYNC instruction. The newer mem-

ory barriers attempt to minimize the amount of pipeline stalls while doing memory synchronization operations.

2.1.2.3 MIPSr3

Architecture

MIPSr3™ is a family of architectures which includes Release 3.0 of the MIPS64 Architecture as well as the ﬁrst

release of the microMIPS64 architecture.

Enhancements included in MIPSr3™ Architecture are:

• The microMIPS

instruction set.

• This instruction set contains both 16-bit and 32-bit sized instructions.

• This mixed size ISA has all of the functionality of MIPS64 while also delivering smaller code sizes.

• microMIPS is assembler source code compatible with MIPS64.

• microMIPS replaces the MIPS16e

ASE.

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