BCM5396单芯片千兆交换机数据表

BCM5396

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"BCM5396是一款由Broadcom Limited（AVGO）推出的单芯片16端口串行千兆交换机，具有低功耗和低成本特性，适用于桌面交换解决方案或WebSmart应用。该器件集成了高速交换系统的所有功能，包括包缓冲、媒体访问控制器（MACs）、地址管理及非阻塞交换控制器，并采用0.13微米CMOS工艺制造，符合IEEE 802.3系列标准，确保与所有行业标准以太网、快速以太网和千兆以太网设备兼容。BCM5396还包括1.25G SerDes接口，减少了板级空间需求，16个端口通过SGMII接口与外部千兆收发器连接。" 详细知识点： 1. **BCM5396**：这是 Broadcom Limited 设计的一款单芯片16端口串行千兆交换机，型号为 BCM5396，其主要特点是低功耗和低成本，适合在桌面型交换机或WebSmart应用中使用。 2. **单芯片集成**：BCM5396 集成了多种功能于一身，包括高速交换系统、包缓冲、MACs、地址管理和非阻塞交换控制器。这种高度集成的设计减少了对外部组件的需求，提高了系统的效率和可靠性。 3. **16个端口**：该设备提供了16个10/100/1000Mbps（即千兆以太网）的接口，每个端口都配备1.25G SerDes（串行 Gigabit Media Independent Interface），能够与外部的千兆物理层（PHY）设备或光纤模块连接。 4. **1.25G SerDes**：SerDes（串行/解串器）技术使得数据在高速串行链路上传输，而1.25G SerDes则意味着每个端口可以支持1.25Gbps的数据速率，有效地减少了电路板上的布线复杂度和空间占用。 5. **SGMII接口**：SGMII（Serial Gigabit Media Independent Interface）是千兆以太网的串行版本，允许BCM5396与外部的千兆以太网收发器进行通信，提供了灵活的连接选项。 6. **协议兼容性**：BCM5396遵循IEEE 802.3系列标准，包括802.3u（Fast Ethernet）、802.3ab（1000BASE-T）和802.3x流量控制，保证了与所有标准以太网设备的兼容性。同时，它支持MAC控制PAUSE帧和自动协商功能。 7. **地址管理**：BCM5396内置了地址管理功能，这对于在网络中正确地路由数据包至关重要，尤其是在多端口设备中。 8. **非阻塞交换控制器**：这种设计确保了在网络中的数据流不会因为内部资源竞争而被阻塞，提供了一种高效、无延迟的通信环境。 9. **Design Guidelines, Quick Start Guide等**：这些额外的文件可能包含关于如何正确设计和启动基于BCM5396的产品的详细指导，对开发者和系统集成商来说是非常宝贵的参考资料。 BCM5396是一款高度集成的千兆以太网交换机芯片，其特点在于低功耗、小体积和强大的网络处理能力，适用于各种需要高带宽、稳定性和扩展性的网络应用。

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List of FiguresBCM5396 Data Sheet

Broadcom

Single-Chip 16-Port SerDes Gigabit Switch

June 20, 2016 • 5396-DS116-R Page 16

Figure 36: SPI Timings, SS

Asserted During SCK Low................................................................................. 190

Figure 37: EEPROM Timing .......................................................................................................................... 191

Figure 38: 256-Pin FBGA Package Outline Drawing ..................................................................................... 193

List of TablesBCM5396 Data Sheet

Broadcom

Single-Chip 16-Port SerDes Gigabit Switch

June 20, 2016 • 5396-DS116-R Page 17

List of Tables

Table 1: Frame Priority Decision Tree Summary ............................................................................................. 28

Table 2: Bucket Bit Rate .................................................................................................................................. 33

Table 3: Unicast Forward Field Definitions ...................................................................................................... 39

Table 4: Address Table Entry for Unicast Address .......................................................................................... 39

Table 5: Multicast Forward Field Definitions .................................................................................................... 41

Table 6: Address Table Entry for Multicast ARL Address ................................................................................ 41

Table 7: Behavior for Reserved Multicast Addresses ...................................................................................... 42

Table 8: Spanning Tree State .......................................................................................................................... 46

Table 9: SGMII and SerDes Auto-Negotiation ................................................................................................. 54

Table 10: Transmit/Receive Frame Format Over Management Port ............................................................... 56

Table 11: OPCODE Field in BRCM Tag for Management Port Frame............................................................ 57

Table 12: IMP Broadcom TAG RX from CPU .................................................................................................. 57

Table 13: IMP Broadcom TAG TX to CPU....................................................................................................... 58

Table 14: EEPROM_EXT[1:0] Settings ........................................................................................................... 64

Table 15: EEPROM Header Format ................................................................................................................ 65

Table 16: EEPROM Contents .......................................................................................................................... 65

Table 17: Pseudo-PHY MII Register Definitions .............................................................................................. 71

Table 18: MII Management Frame Format ...................................................................................................... 72

Table 19: Serial LED Mode Matrix ................................................................................................................... 73

Table 20: Serial LED Status Types.................................................................................................................. 74

Table 21: Load Meter LED Decode ................................................................................................................. 74

Table 22: I/O Signal Type Definitions .............................................................................................................. 76

Table 23: Signal Descriptions .......................................................................................................................... 77

Table 24: Pin Assignment (Listed by Pin Number) .......................................................................................... 83

Table 25: Pin Assignment (Listed by Signal Name)......................................................................................... 85

Table 26: Global Page Register Map ............................................................................................................... 88

Table 27: Control Registers (Page 00h) .......................................................................................................... 91

Table 28: 10/100/1000 Port Control Register (Page 00h: Address 00h–0Fh) ................................................. 93

Table 29: IMP Port Control Register (Page 00h: Address 10h) ....................................................................... 93

Table 30: Switch Mode Register (Page 00h: Address 20h) ............................................................................. 94

Table 31: LED A Register (Page 00h: Address 24h–25h) ............................................................................... 95

Table 32: New Control Register (Page 00h: Address 3Bh) ............................................................................. 95

Table 33: Reserved Multicast Register (Page 00h: Address 50h) ................................................................... 96

Table 34: Load Meter Update Rate Control Register (Page 00h: Address 51h).............................................. 96

Table 35: Unicast Lookup Failed Forward Map Register (Page 00h: 54h–57h) .............................................. 97

List of TablesBCM5396 Data Sheet

Broadcom

Single-Chip 16-Port SerDes Gigabit Switch

June 20, 2016 • 5396-DS116-R Page 18

Table 36: Multicast Lookup Failed Forward Map Register (Page 00h: Address 58h–5Bh) ............................. 97

Table 37: Port N State Override Register (Page 00h: Address 60–6Fh) ......................................................... 97

Table 38: Port 16 (IMP) State Override Register (Page 00h: Address 70h) .................................................... 98

Table 39: 802.1X Control Register 1 (Page 00h: Address 77h)....................................................................... 98

Table 40: 802.1X Control Register 2 (Page 00h: Address 78h–7Bh) .............................................................. 99

Table 41: SerDes Default Values Register (Page 00h: Address 80h–83h) ..................................................... 99

Table 42: SerDes Select Early Version of CRS and COL Register (Page 00h: Address 84h–85h) ................ 99

Table 43: External PHY Scan Control Register (Page 00h: Address 86h) .................................................... 100

Table 44: Fast Aging Control Register (Page 00h: Address 88h).................................................................. 100

Table 45: Fast Aging Port Register (Page 00h: Address 89h) .......................................................................101

Table 46: Fast Aging VID Register (Page 00h: Address 138d–139d, 8Ah–8Bh)........................................... 101

Table 47: Pause Frame Detection Control Register (Page 00h: Address 90h) ............................................. 102

Table 48: Status Registers (Page 01h).......................................................................................................... 103

Table 49: Link Status Summary Register (Page 01h: Address 00h–03h) ..................................................... 104

Table 50: Link Status Change Register (Page 01h: Address 04h–07h) ........................................................ 104

Table 51: Port Speed Summary Register (Page 01h: Address 08h–0Fh) ..................................................... 104

Table 52: Duplex Status Summary Register (Page 01h: Address 10h–13h) ................................................. 105

Table 53: TX PAUSE Status Summary Register (Page 01h: Address 14h–17h) .......................................... 105

Table 54: RX PAUSE Status Summary Register (Page 01h: Address 18h–1Bh) ......................................... 105

Table 55: Port N PHY Status Register (Page 01h: Address 20–2Fh)............................................................ 106

Table 56: SerDes Signal Detect Status Register (Page 01h: Address 40h) .................................................. 106

Table 57: BIST Status Register (Page 01h, Address 46h) ............................................................................ 106

Table 58: Strap Value Register (Page 01h: Address 70h–73h)..................................................................... 107

Table 59: Management Mode Registers (Page 02h) ..................................................................................... 108

Table 60: Global Management Configuration Register (Page 02h: Address 00h) ......................................... 108

Table 61: Aging Time Control Register (Page 02h: Address 0Ch–0Fh) ........................................................ 109

Table 62: Mirror Capture Control Register (Page 02h: Address 10h–11h).................................................... 109

Table 63: Ingress Mirror Control Register (Page 02h: Address 12h–15h) ..................................................... 110

Table 64: Ingress Mirror Divider Register (Page 02h: Address 16h–17h) ..................................................... 110

Table 65: Egress Mirror Control Register (Page 02h: Address 1Ch–1Fh)..................................................... 110

Table 66: Model ID Register (Page 02h: Address 30h) ................................................................................. 111

Table 67: Revision ID Register (Page 02h: Address 40h) ............................................................................. 111

Table 68: ARL Control Registers (Page 04h) ................................................................................................ 112

Table 69: Global ARL Configuration Register (Page 04h: Address 00h)....................................................... 112

Table 70: BPDU Multicast Address Register (Page 04h: Address 04h–09h) ................................................ 113

Table 71: Multiport Address 1 Register (Page 04h: Address 10h–15h)......................................................... 113

Table 72: Multiport Vector 1 Register (Page 04h: Address 16h–19h) ........................................................... 113

List of TablesBCM5396 Data Sheet

Broadcom

Single-Chip 16-Port SerDes Gigabit Switch

June 20, 2016 • 5396-DS116-R Page 19

Table 73: Multiport Address 2 Register (Page 04h: Address 20h–25h)......................................................... 114

Table 74: Multiport Vector 2 Register (Page 04h: Address 26h–29h) ........................................................... 114

Table 75: ARL/VLAN Access Registers (Page 05h) ...................................................................................... 114

Table 76: ARL Read/Write Control Register (Page 05h: Address 00h) ......................................................... 115

Table 77: MAC Address Index Register (Page 05h: Address 02h–07h)........................................................ 115

Table 78: VID Index Register (Page 05h: Address 08h–09h)........................................................................ 116

Table 79: ARL MAC/VID Entry 0 Register (Page 05h: Address 10h–17h) .................................................... 116

Table 80: ARL FWD Entry 0 Register (Page 05h: Address 18h–1Bh)........................................................... 116

Table 81: ARL MAC/VID Entry 1 Register (Page 05h: Address 20h–27h) .................................................... 117

Table 82: ARL FWD Entry 1 Register (Page 05h: Address 28h–2Bh)........................................................... 118

Table 83: ARL Search Control Register (Page 05h: Address 30h)................................................................ 119

Table 84: ARL Search Address Register (Page 05h: Address 31h–32h) ...................................................... 119

Table 85: ARL Search MAC/VID Result Register 0 (Page 05h: Address 33h–3Ah)...................................... 120

Table 86: ARL Search Result Register 0 (Page 05h: Address 3Bh–3Eh) ..................................................... 120

Table 87: ARL Search MAC/VID Result Register 1 (Page 05h: Address 40h–47h) ...................................... 121

Table 88: ARL Search Result Register 1 (Page 05h: Address 48h–4Bh)...................................................... 121

Table 89: VLAN Table Read/Write Control Register (Page 05h: Address 60h)............................................. 122

Table 90: VLAN Table Address Index Register (Page 05h: Address 61h–62h) ............................................ 122

Table 91: VLAN Table Entry Register (Page 05h: Address 63h–6Ah) .......................................................... 123

Table 92: Flow Control Registers (Page 0Ah) ............................................................................................... 123

Table 93: Internal SerDes Registers Page Descriptions 10h–1Fh ................................................................ 127

Table 94: Internal SerDes Registers Page 10h–1Fh ..................................................................................... 127

Table 95: MII Control (Page 10h–1Fh: Address 00h–01h) ............................................................................128

Table 96: MII Status (Page 10h–1Fh: Address 02h–03h).............................................................................. 129

Table 97: Auto-Negotiation Advertisement (Page 10h–1Fh: Address 08h–09h) ........................................... 131

Table 98: Auto-Negotiation Link Partner Ability (Page 10h–1Fh: Address 0Ah–0Bh) ................................... 131

Table 99: Auto-Negotiation Expansion (Page 10h–1Fh: Address 0Ch–0Dh) ................................................ 133

Table 100: Extended Status (Page 10h–1Fh: Address 1Eh–1Fh)................................................................. 133

Table 101: SerDes/SGMII Control1 (Page 10h–1Fh: Address 20h–21h, Block 0) ........................................ 133

Table 102: Analog Transmit Register (Page 10h ~ 1Fh: Address 20h ~ 21h, Block 1) ................................. 136

Table 103: SerDes/SGMII Control 2 (Page 10h–1Fh: Address 22h–23h) ..................................................... 136

Table 104: SerDes/SGMII Control 3 (Page 10h–1Fh: Address 24h–25h) ..................................................... 137

Table 105: SerDes/SGMII Status 1 (Page 10h–1Fh: Address 28h–29h) ...................................................... 138

Table 106: SerDes/SGMII Status 2 (Page 10h–1Fh: Address 2Ah–2Bh)...................................................... 139

Table 107: SerDes/SGMII Status 3 (Page 10h–1Fh: Address 2Ch–2Dh) ..................................................... 140

Table 108: BER/CRC Error Counter Register (Page 10h ~ 1Fh: Address 2Eh ~ 2Fh).................................. 141

Table 109: PRBS Control Register (Page 10h ~ 1Fh: Address 30h ~ 31h)................................................... 141

List of TablesBCM5396 Data Sheet

Broadcom

Single-Chip 16-Port SerDes Gigabit Switch

June 20, 2016 • 5396-DS116-R Page 20

Table 110: PRBS Status Register (Page 10h ~ 1Fh: Address 32h ~ 33h) .................................................... 142

Table 111: Pattern Generator Control Register (Page 10h ~ 1Fh: Address 34h ~ 35h)................................ 142

Table 112: Pattern Generator Control Register (Page 10h ~ 1Fh: Address 36h ~ 37h)................................ 143

Table 113: Pattern Generator Control Register (Page 10h ~ 1Fh: Address 36h ~ 37h)................................ 144

Table 114: Force Transmit 1 Register (Page 10h ~ 1Fh: Address 3Ah ~ 3Bh) ............................................. 144

Table 115: Block Address (Pages 10h–1Fh: Address 3Eh ~ 3Fh) ................................................................ 144

Table 116: QoS Registers (Page 30h) ........................................................................................................... 145

Table 117: QoS Global Control Register (Page 30h: Address 00h) .............................................................. 146

Table 118: QoS Threshold Control Register (Page 30h: Address 01h–02h)................................................. 147

Table 119: QoS 1P Enable Register (Page 30h: Address 04h–07h)............................................................. 147

Table 120: QoS DiffServ Enable Register (Page 30h: Address 08h–0Bh) .................................................... 147

Table 121: 1P/1Q Priority Map Register (Page 30h: Address 10h–13h) ....................................................... 147

Table 122: DiffServ Priority Map 0 Register (Page 30h: Address 30h–35h).................................................. 148

Table 123: DiffServ Priority Map 1 Register (Page 30h: Address 36h–3Bh) ................................................. 149

Table 124: DiffServ Priority Map 2 Register (Page 30h: Address 3Ch–41h) ................................................. 150

Table 125: DiffServ Priority Map 3 Register (Page 30h: Address 42h–47h).................................................. 150

Table 126: QoS Port Control N Register (Page 30h: Address 50h–71h)....................................................... 151

Table 127: QoS TX Control Register (Page 30h: Address 80h) .................................................................... 152

Table 128: Queue N Weight Register (Page 30h: Address 81h–84h) ........................................................... 152

Table 129: EtherType Priority Control Register (Page 30h: Address 88h–8Bh)............................................ 153

Table 130: Enable Traffic Priority Remap Control Register (Page 30h: Address A0h–A3h) ......................... 153

Table 131: Traffic Priority Remap Register (Page 30h: Address A4h) .......................................................... 153

Table 132: Page 31h Port-based VLAN Registers ........................................................................................ 154

Table 133: Port VLAN Control Register (Pages: 31h, Address 0h–43h) ....................................................... 154

Table 134: Trunking Registers (Page 32h) .................................................................................................... 154

Table 135: MAC Trunk Control Register (Pages: 32h, Address 1h) .............................................................. 156

Table 136: Trunk Group Register [0:3] (Pages: 32h, Address 90h–9Fh) ...................................................... 157

Table 137: QoS Registers (Page 34h) ........................................................................................................... 158

Table 138: Global Control 0 Register (Pages 34h: Address 00h).................................................................. 158

Table 139: Global Control 1 Register (Pages 34h: Address 01h).................................................................. 159

Table 140: Global Control 2 Register (Pages 34h: Address 02h).................................................................. 160

Table 141: Global Control 3 Register (Pages 34h: Address 03h–06h).......................................................... 160

Table 142: Global Control 4 Register (Pages 34: Address 07h) .................................................................... 160

Table 143: Global Control 5 Register (Pages 34h: Address 08h).................................................................. 161

Table 144: New Priority Map Register (Pages 34h: Address 0C–0Fh).......................................................... 162

Table 145: Port N Default 802.1Q Tag Register (Pages 34h: Address 10h–31h) ......................................... 162

Table 146: Jumbo Frame Control Registers (Page 40h) ............................................................................... 163

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