数字设计基础与实践：探索硬件世界

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"Digital Design Principles and Practices,3rd （数字设计原理与实践(第三版)英文版）" 本书《数字设计原理与实践》是John F. Wakerly所著的第三版，由Prentice Hall在1999年出版，以PDF格式提供，无加密。该书主要针对的是计算机科学和电子工程领域的学生，无论是对计算机硬件有疑问的软件专业学生，还是对模拟电子和电路设计有一定了解的电气工程学生，都可以从中受益。 1.1 关于数字系统本书的开篇介绍了数字系统的基本概念。数字设计是理解和创建数字电路及子系统的基石，这些电路和子系统构成了我们现代电子设备的核心。作者旨在从一个相对基础的水平出发，帮助读者理解如何设计这些复杂的系统。 1.2 数字逻辑书中会深入讲解数字逻辑的基础，包括布尔代数、基本逻辑门（如AND、OR、NOT）、组合逻辑电路以及时序逻辑电路的设计。这些基础知识是数字设计的根基，能够帮助读者理解如何用简单的逻辑元素构建复杂的逻辑功能。 1.3 数字数据表示数字数据在计算机中是如何表示的也是本书的重要内容。这包括二进制、八进制、十六进制等不同进制转换，以及位、字节、字的构成，还有数值、字符、浮点数的存储方式。 1.4 芯片和集成电路书中会介绍不同类型的半导体材料和器件，如二极管、晶体管，以及它们在数字电路中的应用。此外，大规模集成电路（VLSI）和微处理器的工作原理也会被讨论，这将使读者理解现代计算机硬件的内部运作。 1.5 数字电路设计方法在理论基础上，作者会分享实际的数字电路设计方法，包括硬件描述语言（HDL，如Verilog和VHDL）的使用，以及如何通过逻辑综合和布局布线工具将设计转化为实际电路。 1.6 实验与项目为了巩固理论知识，书中通常包含实验指导和项目建议，鼓励读者动手实践，通过实际操作来加深对理论的理解。 1.7 当前技术趋势考虑到技术的快速发展，书中会讨论当前的数字设计趋势，如可编程逻辑器件（FPGA）、嵌入式系统、高速通信接口和低功耗设计等，让读者了解数字设计领域的最新发展。通过本书的学习，读者不仅可以掌握数字设计的基本原理，还能了解实际设计过程中的挑战和解决方案，以及如何与不断变化的技术环境保持同步。作者采用的亲和性叙述方式，旨在让读者感觉如同共同探索学习过程，从而更有效地掌握这一领域知识。

16 Chapter 1 Introduction

DO NOT COPY

Proponents of one approach or the other used to get into “religious” argu-

ments over which way was better, but the largest manufacturer of large

programmable logic devices, Xilinx Corporation, acknowledges that there is a

place for both approaches and manufactures both types of devices. What’s more

important than chip architecture is that both approaches support a style of design

in which products can be moved from design concept to prototype and produc-

tion in a very period of time short time.

Also important in achieving short “time-to-market” for all kinds of PLD-

based products is the use of HDLs in their design. Languages like ABEL and

VHDL, and their accompanying software tools, allow a design to be compiled,

synthesized, and downloaded into a PLD, CPLD, or FPGA literally in minutes.

The power of highly structured, hierarchical languages like VHDL is especially

important in helping designers utilize the hundreds of thousands or millions of

gates that are provided in the largest CPLDs and FPGAs.

1.8 Application-Specific ICs

Perhaps the most interesting developments in IC technology for the average

digital designer are not the ever-increasing chip sizes, but the ever-increasing

opportunities to “design your own chip.” Chips designed for a particular, limited

product or application are called

semicustom ICs

application-specific ICs

(ASICs)

. ASICs generally reduce the total component and manufacturing cost of

a product by reducing chip count, physical size, and power consumption, and

they often provide higher performance.

The

nonrecurring engineering (NRE) cost

for designing an ASIC can

exceed the cost of a discrete design by $5,000 to $250,000 or more. NRE charges

are paid to the IC manufacturer and others who are responsible for designing the

PLD PLD PLD PLD

Programmable Interconnect

(a) (b) = logic block

Figure 1-6

Large programmable-logic-device scaling approaches: (a) CPLD; (b) FPGA.

semicustom IC

application-specific IC

(ASIC)

nonrecurring

engineering (NRE)

cost

Section 1.8 Application-Specific ICs 17

DO NOT COPY

internal structure of the chip, creating tooling such as the metal masks for manu-

facturing the chips, developing tests for the manufactured chips, and actually

making the first few sample chips.

The NRE cost for a typical, medium-complexity ASIC with about 100,000

gates is $30–$50,000. An ASIC design normally makes sense only when the

NRE cost can be offset by the per-unit savings over the expected sales volume of

the product.

The NRE cost to design a

custom LSI

chip—a chip whose functions, inter-

nal architecture, and detailed transistor-level design is tailored for a specific

customer—is very high, $250,000 or more. Thus, full custom LSI design is done

only for chips that have general commercial application or that will enjoy very

high sales volume in a specific application (e.g., a digital watch chip, a network

interface, or a bus-interface circuit for a PC).

To reduce NRE charges, IC manufacturers have developed libraries of

standard cells

including commonly used MSI functions such as decoders,

registers, and counters, and commonly used LSI functions such as memories,

programmable logic arrays, and microprocessors. In a

standard-cell design

, the

logic designer interconnects functions in much the same way as in a multichip

MSI/LSI design. Custom cells are created (at added cost, of course) only if abso-

lutely necessary. All of the cells are then laid out on the chip, optimizing the

layout to reduce propagation delays and minimize the size of the chip. Minimiz-

ing the chip size reduces the per-unit cost of the chip, since it increases the

number of chips that can be fabricated on a single wafer. The NRE cost for a

standard-cell design is typically on the order of $150,000.

Well, $150,000 is still a lot of money for most folks, so IC manufacturers

have gone one step further to bring ASIC design capability to the masses. A

gate

array

is an IC whose internal structure is an array of gates whose interconnec-

tions are initially unspecified. The logic designer specifies the gate types and

interconnections. Even though the chip design is ultimately specified at this very

low level, the designer typically works with “macrocells,” the same high-level

functions used in multichip MSI/LSI and standard-cell designs; software

expands the high-level design into a low-level one.

The main difference between standard-cell and gate-array design is that the

macrocells and the chip layout of a gate array are not as highly optimized as

those in a standard-cell design, so the chip may be 25% or more larger, and

therefore may cost more. Also, there is no opportunity to create custom cells in

the gate-array approach. On the other hand, a gate-array design can be complet-

ed faster and at lower NRE cost, ranging from about $5000 (what you’re told

initially) to $75,000 (what you find you’ve spent when you’re all done).

The basic digital design methods that you’ll study throughout this book

apply very well to the functional design of ASICs. However, there are additional

opportunities, constraints, and steps in ASIC design, which usually depend on

the particular ASIC vendor and design environment.

custom LSI

standard cells

standard-cell design

gate array

18 Chapter 1 Introduction

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1.9 Printed-Circuit Boards

An IC is normally mounted on a

printed-circuit board (PCB)

[or

printed-wiring

board (PWB)

] that connects it to other ICs in a system. The multilayer PCBs

used in typical digital systems have copper wiring etched on multiple, thin layers

of fiberglass that are laminated into a single board about 1/16 inch thick.

Individual wire connections, or

PCB traces

are usually quite narrow, 10 to

25 mils in typical PCBs. (A

mil

is one-thousandth of an inch.) In

fine-line

PCB

technology, the traces are extremely narrow, as little as 4 mils wide with 4-mil

spacing between adjacent traces. Thus, up to 125 connections may be routed in a

one-inch-wide band on a single layer of the PCB. If higher connection density is

needed, then more layers are used.

Most of the components in modern PCBs use

surface-mount technology

(SMT)

. Instead of having the long pins of DIP packages that poke through the

board and are soldered to the underside, the leads of SMT IC packages are bent

to make flat contact with the top surface of the PCB. Before such components

are mounted on the PCB, a special “solder paste” is applied to contact pads on

the PCB using a stencil whose hole pattern matches the contact pads to be

soldered. Then the SMT components are placed (by hand or by machine) on the

pads, where they are held in place by the solder paste (or in some cases, by glue).

Finally, the entire assembly is passed through an oven to melt the solder paste,

which then solidifies when cooled.

Surface-mount component technology, coupled with fine-line PCB tech-

nology, allows extremely dense packing of integrated circuits and other

components on a PCB. This dense packing does more than save space. For very

high-speed circuits, dense packing goes a long way toward minimizing adverse

analog phenomena, including transmission-line effects and speed-of-light

limitations.

To satisfy the most stringent requirements for speed and density,

multichip

modules (MCMs)

have been developed. In this technology, IC dice are not

mounted in individual plastic or ceramic packages. Instead, the IC dice for a

high-speed subsystem (say, a processor and its cache memory) are bonded

directly to a substrate that contains the required interconnections on multiple

layers. The MCM is hermetically sealed and has its own external pins for power,

ground, and just those signals that are required by the system that contains it.

1.10 Digital-Design Levels

Digital design can be carried out at several different levels of representation and

abstraction. Although you may learn and practice design at a particular level,

from time to time you’ll need to go up or down a level or two to get the job done.

Also, the industry itself and most designers have been steadily moving to higher

levels of abstraction as circuit density and functionality have increased.

rinted-circuit board

(PCB)

rinted-wiring board

(PWB)

PCB traces

mil

ine-line

surface-mount

technology (SMT)

multichip module

(MCM)

Section 1.10 Digital-Design Levels 19

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The lowest level of digital design is device physics and IC manufacturing

processes. This is the level that is primarily responsible for the breathtaking

advances in IC speed and density that have occurred over the past decades. The

effects of these advances are summarized in

Moore’s Law

, first stated by Intel

founder Gordon Moore in 1965: that the number of transistors per square inch in

an IC doubles every year. In recent years, the rate of advance has slowed down to

doubling about every 18 months, but it is important to note that with each dou-

bling of density has also come a doubling of speed.

This book does not reach down to the level of device physics and IC

processes, but you need to recognize the importance of that level. Being aware of

likely technology advances and other changes is important in system and

product planning. For example, decreases in chip geometries have recently

forced a move to lower logic-power-supply voltages, causing major changes in

the way designers plan and specify modular systems and upgrades.

In this book, we jump into digital design at the transistor level and go all

the way up to the level of logic design using HDLs. We stop short of the next

level, which includes computer design and overall system design. The “center”

of our discussion is at the level of functional building blocks.

To get a preview of the levels of design that we’ll cover, consider a simple

design example. Suppose you are to build a “multiplexer” with two data input

bits,

and

, a control input bit

, and an output bit

. Depending on the value

, 0 or 1, the circuit is to transfer the value of either

to the output

. This

idea is illustrated in the “switch model” of Figure 1-7. Let us consider the design

of this function at several different levels.

Although logic design is usually carried out at higher level, for some func-

tions it is advantageous to optimize them by designing at the transistor level. The

multiplexer is such a function. Figure 1-8 shows how the multiplexer can be

designed in “CMOS” technology using specialized transistor circuit structures

oore’s Law

Figure 1-7

Switch model for

multiplexer function.

Figure 1-8

Multiplexer design using

CMOS transmission gates.

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