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首页Apple Macbook A1181 13英寸电路原理图详解
"Apple Macbook A1181 13 的电路原理图是一份详细的技术文档,通常包含了这款苹果电脑内部所有电子组件的布局、连接关系以及工作原理的图形化表示。这份文档由Apple Inc. 出版,旨在帮助维修技术人员、硬件工程师和爱好者理解并维护这款型号的Macbook。电路原理图会列出每个部件的名称、功能,以及它们如何通过导线和电路板互连。此外,还包括了设计变更记录(如REV. A至REV. D的迭代)和不同部门的审批(如Designer、EngAPPD、QAAPPD等),确保了文档的准确性和完整性。"
在电路原理图中,你可以找到以下关键知识点:
1. **组件识别**:每个电路元件都有特定的符号和编号,如电阻、电容、晶体管、集成电路等,这些是理解电路工作原理的基础。
2. **电源管理**:Macbook A1181的电池管理系统是如何与主板交互,如何控制电源输入和分配到各个部件的。
3. **处理器和内存**:中央处理器(CPU)和随机存取存储器(RAM)的连接方式,以及如何与主板上的其他组件通信。
4. **显示系统**:显示屏的接口,包括LVDS或eDP接口,如何将图像数据传输到屏幕。
5. **硬盘和固态驱动器(SSD)**:存储设备的接口类型,如SATA或PCIe,以及数据读写流程。
6. **无线通信**:Wi-Fi和蓝牙模块的位置和连接,以及如何通过天线发送和接收信号。
7. **输入设备**:键盘、触摸板的接口和信号处理,以及它们如何向主板发送用户输入。
8. **音频系统**:内置扬声器和麦克风的工作原理,以及音频信号的处理路径。
9. **USB、Firewire、Thunderbolt和其他I/O接口**:这些接口如何允许用户连接外部设备,以及它们的电源管理和数据传输机制。
10. **散热系统**:风扇和热管的设计,以及温度传感器如何监控和调节设备温度。
11. **电源适配器接口**:电源适配器如何为Macbook供电,以及电压和电流转换的过程。
12. **安全和保护电路**:过压、过流保护电路的原理,以防止设备在异常情况下受损。
这份电路原理图对于故障排查、硬件升级或定制化改造非常有价值。通过仔细研究,不仅可以了解Macbook A1181的内部构造,还能学习到电子产品设计的基本原则和技术。不过,由于涉及到Apple的知识产权,使用和分享这些信息时必须遵循协议,保持文档的保密性。
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H_D0*
H_D3*
H_D2*
H_D33*
H_D34*
H_D35*
H_D1*
H_D4*
H_D10*
H_A4*
H_A5*
H_A6*
H_A7*
H_A8*
H_A9*
H_A10*
H_A11*
H_A12*
H_A13*
H_A14*
H_A15*
H_A16*
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H_A20*
H_A21*
H_A22*
H_A23*
H_A24*
H_A25*
H_A26*
H_A27*
H_A28*
H_A29*
H_A30*
H_A31*
H_A32*
H_A33*
H_A34*
H_A35*
H_ADS*
H_ADSTB0*
H_ADSTB1*
H_A3*
H_D7*
H_D8*
H_D9*
H_D11*
H_D12*
H_D13*
H_D14*
H_D15*
H_D16*
H_D17*
H_D18*
H_D19*
H_D20*
H_D21*
H_D22*
H_D23*
H_D25*
H_D26*
H_D27*
H_D28*
H_D29*
H_D30*
H_D32*
H_D36*
H_D37* H_BNR*
H_D38*
H_BPRI*
H_D39*
H_D40*
H_DEFER*
H_D41*
H_DBSY*
H_D42*
H_D43*
H_D44*
H_DPWR*
H_D45*
H_DRDY*
H_D46* H_HIT*
H_D47*
H_HITM*
H_D48*
H_LOCK*
H_TRDY*
H_D51*
H_D52*
H_D53*
H_DINV0*
H_D54*
H_DINV1*
H_D55*
H_DINV2*
H_D56*
H_DINV3*
H_D57*
H_D58*
H_DSTBN0*
H_D59*
H_DSTBN1*
H_D60*
H_DSTBN2*
H_D61*
H_DSTBN3*
H_D62*
H_D63*
H_DSTBP0*
H_DSTBP1*
H_DSTBP2*
H_SWING
H_RCOMP
H_REQ0*
H_SCOMP H_REQ1*
H_SCOMP*
H_REQ2*
H_REQ3*
H_CPURST*
H_REQ4*
H_CPUSLP*
H_RS0*
H_RS1*
H_AVREF
H_RS2*
H_DVREF
H_D5*
H_D6*
H_D31*
H_BREQ*
H_D24*
H_D49*
H_D50*
H_DSTBP3*
HPLL_CLK
HPLL_CLK*
HOST
(1 OF 10)
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APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
9D8
70C3
9D8
70C3
9C8
70C3
9D6
70D3
9D6
70D3
9D6
70D3
9D6
70D3
9D6
70D3
9B2
70D3
9D6
70D3
9D8
70C3
X5R
0.1uF
10%
16V
402
2
1
C1425
2.0K
MF-LF
1%
1/16W
402
2
1
R1426
1K
MF-LF
1%
1/16W
402
2
1
R1425
9C4
70D3
9B4
70C3
9C2
70C3
9B2
70C3
9C4
70D3
9B4
70C3
9D8
70C3
9C2
70C3
9B2
70C3
9C4
70D3
9B4
70C3
9C2
70C3
9B2
70C3
9C6
70D3
9C6
70D3
9D6
70D3
9D8
70C3
9D6
70D3
9D6
70D3
9D6
70D3
9D8
70C3
9D8
70C3
9D8
70C3
9D8
70C3
9C8
70C3
9D8
70C3
54.9
MF-LF
1%
1/16W
402
2
1
R1420
24.9
MF-LF
1%
1/16W
402
2
1
R1415
221
MF-LF
1%
1/16W
402
2
1
R1410
100
MF-LF
1%
1/16W
402
2
1
R1411
X5R
0.1uF
10%
16V
402
2
1
C1410
9D8
70C3
OMIT
CRESTLINE
FCBGA
AM7
AM5
B7
B3
W2
W1
D8
D7
E12
B12
H13
A11
E13
M14
C2
G10
C6
E4
A9
AJ10
AC2
K2
L7
AH11
AD2
K3
M7
K7
H8
AE13
AD13
L2
K5
D6
C10
H2
N8
F3
AH13
AH2
AJ3
AE5
G4
AJ2
AJ7
AE7
AJ6
AH5
AJ5
AH12
AE11
AE9
AJ14
H3
AH8
AJ9
AG3
AC5
AE2
AC6
Y3
AB1
AD7
AB2
H7
AC11
AD11
AC14
AC7
AC9
AD9
AE3
AD12
N1
W3
M6
P4
Y9
Y7
N2
W9
W6
N3
N5
J1
M3
G7
V4
Y8
W10
M2
K9
P13
H5
N9
N12
M10
G2
E2
E5
B6
F12
E8
C8
B9
G20
H17
G12
L13
F16
C15
M11
C11
B11
N19
B19
A19
C18
E17
B15
J13
B17
E19
B18
J19
N16
M17
D17
L19
H20
B16
R17
P15
K19
B14
J17
L16
B13
K16
C14
G17
U1400
9C8
70C3
9C8
70C3
9C8
70C3
9C8
70C3
9C8
70C3
54.9
MF-LF
1%
1/16W
402
2
1
R1421
9D6
70D3
29D3 75C3
29D3 75C3
9D6
12B570D3
9A2
70B3
9C8
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9B4
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9D8
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9C2
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9B2
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9D6
70D3
SYNC_DATE=10/30/2006
NB CPU Interface
051-7559
H
106
14
SYNC_MASTER=T9_MLB
=PP1V25R1V05_S0_FSB_NB
FSB_D_L<47>
FSB_D_L<3>
FSB_D_L<2>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<1>
FSB_D_L<10>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<11>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<32>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<42>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<48>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
NB_FSB_SCOMP
NB_FSB_SCOMP_L
FSB_CPURST_L
FSB_CPUSLP_L
FSB_D_L<6>
FSB_D_L<31>
FSB_D_L<24>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<12>
FSB_D_L<43>
FSB_D_L<5>
FSB_D_L<4>
FSB_D_L<0>
FSB_D_L<38>
FSB_D_L<41>
FSB_D_L<59>
NB_FSB_SWING
NB_FSB_RCOMP
NB_FSB_VREF
FSB_A_L<3>
FSB_A_L<6>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<11>
FSB_A_L<10>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<32>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
FSB_ADS_L
FSB_ADSTB_L<0>
FSB_ADSTB_L<1>
FSB_BPRI_L
FSB_BNR_L
FSB_BREQ0_L
FSB_DEFER_L
FSB_DBSY_L
FSB_DPWR_L
FSB_CLK_NB_P
FSB_CLK_NB_N
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_TRDY_L
FSB_LOCK_L
FSB_DINV_L<0>
FSB_DINV_L<1>
FSB_DINV_L<2>
FSB_DINV_L<3>
FSB_DSTB_L_N<0>
FSB_DSTB_L_N<1>
FSB_DSTB_L_N<2>
FSB_DSTB_L_N<3>
FSB_DSTB_L_P<0>
FSB_DSTB_L_P<1>
FSB_DSTB_L_P<2>
FSB_DSTB_L_P<3>
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
FSB_RS_L<1>
FSB_RS_L<0>
FSB_RS_L<2>
29C6 29B6
7C7
BI
BI
BI
BI
9C8
70C3
9C8
70C3
70C3
9C8
70C3
9C8
9C8
9C8
E17
FSB_A_L<26>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<29>
FSB_A_L<29>
FSB_A_L<32>
FSB_A_L<32>
FSB_A_L<30>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<31>
FSB_A_L<33>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<34>
FSB_A_L<35>
FSB_A_L<35>
FSB_ADS_L
FSB_ADS_L
FSB_ADSTB_L<0>
FSB_ADSTB_L<0>
FSB_ADSTB_L<1>
FSB_ADSTB_L<1>
FSB_BNR_L
FSB_BNR_L
H_A30*
H_A31*
H_A32*
H_A33*
H_A34*
H_ADS*
H_ADSTB0*
H_ADSTB1*
H_D37* H_BNR*
F12
G12
H_D34*
H_D35*
H_ADSTB1*
H_D36*
H_D37* H_BNR*
H_D38*
H_BPRI*
H_D39*
H_D40*
H_DEFER*
H_D41*
H_DBSY*
H_D43*
H_D44*
H_DPWR*
H_D45*
H_D46*
H_D47*
H_BREQ*
HPLL_CLK
HPLL_CLK*
AE9
AJ14
AH8
AJ9
AB1
AD7
FSB_D_L<40>
FSB_D_L<40>
FSB_D_L<42>
FSB_D_L<42>
FSB_D_L<44>
FSB_D_L<43>
FSB_D_L<43>
FSB_D_L<41>
FSB_D_L<41>
BI
BI
BI
BI
9C2
70C3
70C3
9C2
70C3
9C2
FSB_D_L<47>
FSB_D_L<47>
FSB_D_L<48>
FSB_D_L<48>
FSB_D_L<51>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<58>
FSB_D_L<49>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<50>
FSB_D_L<47>
FSB_D_L<47>
FSB_D_L<44>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<46>
FSB_D_L<48>
FSB_D_L<48>
FSB_D_L<49>
BI
BI
BI
BI
70C3
9B2
9B2
9B2
70C3
9B2
70C3
9B2
70C3
9B2
70C3
70C3
R1420
MF-LF
1/16W
402
R1410
1
54.9
MF-LF
1%
1/16W
402
1
R1420
54.9
1%
1/16W
2
IN
IN
OUT
IN
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
BI
L_BKLT_CTRL
L_VDD_EN
PEG_TX15*
PEG_TX14*
PEG_TX13*
PEG_TX12*
PEG_TX11*
PEG_TX10*
PEG_TX9*
PEG_TX8*
PEG_TX7*
PEG_TX6*
PEG_TX5*
PEG_TX4*
PEG_TX3*
PEG_TX2*
PEG_TX1*
PEG_TX0*
PEG_TX15
PEG_TX14
PEG_TX13
PEG_TX12
PEG_TX11
PEG_TX10
PEG_TX9
PEG_TX8
PEG_TX7
PEG_TX6
PEG_TX5
PEG_TX4
PEG_TX3
PEG_TX2
PEG_TX1
PEG_TX0
PEG_RX14
PEG_RX15*
PEG_RX14*
PEG_RX13*
PEG_RX12*
PEG_RX11*
PEG_RX15
PEG_RX13
PEG_RX12
PEG_RX11
PEG_RX10
PEG_RX9
PEG_RX8
PEG_RX7
PEG_RX6
PEG_RX5
PEG_RX4
PEG_RX3
PEG_RX2
PEG_RX1
PEG_RX0
PEG_RX10*
PEG_RX9*
PEG_RX8*
PEG_RX7*
PEG_RX6*
PEG_RX5*
PEG_RX4*
PEG_RX3*
PEG_RX2*
PEG_RX1*
PEG_RX0*
PEG_COMPI
PEG_COMPO
CRT_DDC_DATA
L_CTRL_DATA
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA0
LVDSB_DATA2*
LVDSB_DATA1*
LVDSB_DATA0*
LVDSA_DATA2
LVDSA_DATA0
LVDSA_DATA1
LVDSB_CLK*
LVDS_VREFL
LVDS_IBG
TVC_RTN
TVA_RTN
TVB_RTN
TVC_DAC
TVB_DAC
TVA_DAC
CRT_RED*
CRT_RED
CRT_GREEN*
CRT_GREEN
CRT_BLUE*
CRT_BLUE
CRT_VSYNC
CRT_TVO_IREF
CRT_HSYNC
CRT_DDC_CLK
L_BKLT_EN
L_DDC_CLK
TV_DCONSEL0
TV_DCONSEL1
LVDSA_DATA2*
L_DDC_DATA
LVDSA_DATA1*
LVDSA_DATA0*
LVDSB_CLK
LVDSA_CLK
LVDSA_CLK*
LVDS_VREFH
L_CTRL_CLK
LVDS_VBG
VGA
TV
LVDS
(3 OF 10)
PCI-EXPRESS GRAPHICS
BI
BI
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
SDVO_FLDSTALL#
SDVO Alternate Function
SDVO_TVCLKIN#
SDVO_INT#
SDVO_TVCLKIN
SDVO_INT
SDVO_FLDSTALL
SDVOB_GREEN
SDVOB_RED
SDVOC_CLKN
SDVOC_BLUE#
SDVOC_GREEN#
SDVOC_RED#
SDVOB_CLKN
SDVOB_BLUE#
SDVOB_GREEN#
SDVOB_RED#
SDVOB_CLKP
SDVOB_BLUE
SDVOC_CLKP
SDVOC_BLUE
SDVOC_GREEN
SDVOC_RED
If SDVO is used, VCCD_LVDS must remain powered with proper
LVDS Disable
Tie VCC_TX_LVDS and VCCA_LVDS to GND.
TVDAC rails. VCCA_TVx_DAC and VCCA_DAC_BG can
should connect to GND through 75-ohm resistors.
Component: DACA, DACB & DACC
Composite: DACA only
TV-Out Signal Usage:
Can tie the following rails to GND:
VSYNC and CRT_TVO_IREF to GND.
CRT Disable / TV-Out Enable
TV-Out Disable / CRT Enable
Tie TVx_DAC and TVx_RTN to GND. Must power all
Leave GFX_VID<3..0> and GFX_VR_EN as NC.
Tie VCC_AXG and VCC_AXG_NCTF to GND.
Tie VCCA_DPLLA and VCCA_DPLLB to VCC (VCore).
Tie DPLL_REF_CLK and DPLL_REF_SSCLK to GND.
Can also tie CRT_DDC_*, L_CTRL_*, L_DDC_*, SDVO_CTRL_* and
TV_DCONSELx to GND.
Follow instructions for LVDS and CRT & TV-Out Disable above.
Internal Graphics Disable
and filtered at all times!
NOTE: Must keep VDDC_TVDAC powered
VCCD_CRT, VCCD_QDAC and VCC_SYNC.
VCCA_CRT_DAC, VCCA_DAC_BG, VCCA_TVx_DAC,
omit filtering components. Unused DAC outputs
All CRT/TVDAC rails must be powered. All
CRT & TV-Out Disable
Tie TVx_DAC, TVx_RTN, R/R#/G/G#/B/B#, HSYNC,
Tie R/R#/G/G#/B/B#, HSYNC and VSYNC to GND.
share filtering with VCCA_CRT_DAC.
Unused DAC outputs must remain powered, but can
S-Video: DACB & DACC only
Can leave all signals NC if LVDS is not implemented.
decoupling. Otherwise, tie VCCD_LVDS to GND also.
Tie DPLL_REF_CLK* and DPLL_REF_SSCLK* to VCC (VCore).
rails must be filtered except for VCCA_CRT.
8C6
8C6
24.9
1%
1/16W
MF-LF
402
2
1
R1510
67B8
8C6
69B8
69A8
69A8
69D7
69D8
69D7
69A8
8C6
69B8
69A8
67A871C3
FCBGA
CRESTLINE
OMIT
L27
K27
J27
G27
F27
E27
P33
M35
AD39
AC38
W38
Y39
W46
Y47
Y43
W42
T42
U43
R50
R51
N51
N50
U47
T46
AH44
AH43
AE49
AE50
AH39
AG39
AC42
AD43
AC49
AC50
AC46
AD47
U39
T38
N45
M45
W49
Y48
AB51
AB50
Y40
W41
Y44
W45
U40
T41
T50
T49
T45
U44
N47
M47
AG41
AG42
AG45
AH45
AH49
AG49
AG46
AH47
AD40
AC41
AD44
AC45
L51
L50
J51
J50
M43
N43
B45
A45
B47
A47
G44
E44
D44
E42
F49
F48
E51
E50
G51
G50
D46
C45
N40
N41
L43
L41
K40
D35
C37
E40
E39
H39
J40
E33
C32
E29
F29
F33
J29
K29
G35
K33
G32
H32
U1400
12B167A7
12B167A7
69C8
69C8
8C6
8C6
8C6
8C6
8C6
8C6
8D6
68B6 71D3
8C6
8C6
8C6
8C6
8C6
8C6
8C6
8C6
8C6
68B6 71D3
8C6
8B6
8B6
8B6
68C6 71D3
68C6 71D3
8B6
8A6
8B6
8B6
8C6
8B6
8B6
8B6
8B6
8B6
8B6
8B6
8B6
8B6
8B6
8C6
8B6
8B6
8B6
8B6
8B6
8B6
8B6
8B6
8B6
8B6
8C6
68B6 71D3
68B6 71D3
68B6 71D3
68B6 71D3
68C6 71D3
68C6 71D3
67C6
67D8
8C6
67B6
67B6
67B371D3
67B371D3
8D6
8D6
67B271D3
67B271D3
8C6
67B271D3
8D6
8D6
8D6
67B271D3
67B271D3
67B271D3
8D6
8D6
8D6
8C6
69D8
69D8
69D8
69D7
69D7
69D7
69B8
69B8
SYNC_MASTER=T9_MLB
NB PEG / Video Interfaces
051-7559
H
106
15
SYNC_DATE=10/30/2006
=TV_B_RTN
=TV_B_DAC
LVDS_B_DATA_N<2>
LVDS_B_DATA_N<1>
LVDS_CTRL_DATA
LVDS_CTRL_CLK
TP_LVDS_VBG
PEG_D2R_P<9>
PEG_D2R_P<11>
PEG_D2R_P<10>
PP1V05_S0_NB_VCCPEG
PEG_D2R_N<1>
PEG_D2R_N<6>
TP_LVDS_VREFH
LVDS_A_CLK_N
LVDS_A_CLK_P
LVDS_B_CLK_P
LVDS_A_DATA_N<0>
LVDS_A_DATA_N<1>
LVDS_A_DATA_N<2>
TV_DCONSEL<1>
TV_DCONSEL<0>
LVDS_BKLT_EN
CRT_DDC_CLK
=CRT_HSYNC_R
=CRT_TVO_IREF
=CRT_VSYNC_R
=CRT_BLUE
=CRT_BLUE_L
=CRT_GREEN
=CRT_GREEN_L
=CRT_RED
=CRT_RED_L
=TV_A_DAC
=TV_C_DAC
=TV_A_RTN
=TV_C_RTN
LVDS_IBG
TP_LVDS_VREFL
LVDS_B_CLK_N
LVDS_A_DATA_P<1>
LVDS_A_DATA_P<0>
LVDS_A_DATA_P<2>
LVDS_B_DATA_N<0>
LVDS_B_DATA_P<0>
LVDS_B_DATA_P<2>
LVDS_B_DATA_P<1>
CRT_DDC_DATA
PEG_COMP
PEG_D2R_N<0>
PEG_D2R_N<2>
PEG_D2R_N<3>
PEG_D2R_N<4>
PEG_D2R_N<5>
PEG_D2R_N<7>
PEG_D2R_N<8>
PEG_D2R_N<9>
PEG_D2R_N<10>
PEG_D2R_P<0>
PEG_D2R_P<1>
PEG_D2R_P<2>
PEG_D2R_P<3>
PEG_D2R_P<4>
PEG_D2R_P<5>
PEG_D2R_P<6>
PEG_D2R_P<7>
PEG_D2R_P<8>
PEG_D2R_P<12>
PEG_D2R_P<13>
PEG_D2R_P<15>
PEG_D2R_N<11>
PEG_D2R_N<12>
PEG_D2R_N<13>
PEG_D2R_N<14>
PEG_D2R_N<15>
PEG_D2R_P<14>
PEG_R2D_C_P<0>
PEG_R2D_C_P<1>
PEG_R2D_C_P<2>
PEG_R2D_C_P<3>
PEG_R2D_C_P<4>
PEG_R2D_C_P<5>
PEG_R2D_C_P<6>
PEG_R2D_C_P<7>
PEG_R2D_C_P<8>
PEG_R2D_C_P<9>
PEG_R2D_C_P<10>
PEG_R2D_C_P<11>
PEG_R2D_C_P<12>
PEG_R2D_C_P<13>
PEG_R2D_C_P<14>
PEG_R2D_C_P<15>
PEG_R2D_C_N<0>
PEG_R2D_C_N<1>
PEG_R2D_C_N<2>
PEG_R2D_C_N<3>
PEG_R2D_C_N<4>
PEG_R2D_C_N<5>
PEG_R2D_C_N<6>
PEG_R2D_C_N<7>
PEG_R2D_C_N<8>
PEG_R2D_C_N<9>
PEG_R2D_C_N<10>
PEG_R2D_C_N<11>
PEG_R2D_C_N<12>
PEG_R2D_C_N<13>
PEG_R2D_C_N<14>
PEG_R2D_C_N<15>
LVDS_BKLT_CTL
LVDS_DDC_CLK
LVDS_DDC_DATA
LVDS_VDD_EN
20D318B3
IN
SDVO_TVCLKIN
SDVO_INT
SDVO_FLDSTALL
8C6
8C6
8C6
IN
IN
8C6
68B6 71D3
8C6
PEG_D2R_P<9>
PEG_D2R_P<0>
PEG_D2R_P<0>
PEG_D2R_P<1>
PEG_D2R_P<1>
PEG_D2R_P<2>
PEG_D2R_P<2>
PEG_D2R_P<3>
PEG_D2R_P<3>
PEG_D2R_P<4>
PEG_D2R_P<4>
PEG_D2R_P<5>
PEG_D2R_P<5>
PEG_D2R_P<6>
PEG_D2R_P<6>
PEG_D2R_P<7>
PEG_D2R_P<7>
PEG_D2R_P<8>
PEG_D2R_P<8>
PEG_D2R_N<13>
PEG_D2R_N<13>
PEG_D2R_N<14>
PEG_D2R_N<14>
PEG_D2R_N<15>
PEG_D2R_N<15>
PEG_RX14
PEG_RX15
PEG_RX13
PEG_RX12
PEG_RX11
PEG_RX10
PEG_RX7
PEG_RX6
PEG_RX5
U39
N45
W45
T49
AH47
AC41
PEG_D2R_P<9>
PEG_D2R_P<9>
PEG_D2R_P<11>
PEG_D2R_P<11>
PEG_D2R_P<10>
PEG_D2R_P<10>
PEG_D2R_P<6>
PEG_D2R_P<6>
PEG_D2R_P<7>
PEG_D2R_P<7>
PEG_D2R_P<8>
PEG_D2R_P<8>
PEG_D2R_P<12>
PEG_D2R_P<12>
PEG_D2R_P<13>
PEG_D2R_P<13>
LVDSB_DATA2*
LVDSB_DATA1*
LVDSB_DATA0*
PEG_TX4*
PEG_TX3*
PEG_TX2*
PEG_TX1*
PEG_TX0*
PEG_RX15
PCI-EXPRESS GRAPHICS
TVC_RTN
TVA_RTN
TVB_RTN
TVC_DAC
TVA_DAC
TV_DCONSEL0
TV
PCI-EXPRESS GRAPHICS
L27
J27
OUT
=TV_C_DAC
=TV_C_DAC
=TV_A_RTN
=TV_A_RTN
OUT
OUT
OUT
69A8
=CRT_BLUE
=CRT_BLUE
=CRT_BLUE_L
=CRT_BLUE_L
=CRT_GREEN
=CRT_GREEN
=CRT_GREEN_L
=CRT_GREEN_L
=CRT_RED
=CRT_RED
=TV_B_RTN
=TV_B_RTN
TV_DCONSEL<1>
TV_DCONSEL<1>
TV_DCONSEL<0>
TV_DCONSEL<0>
=TV_A_RTN
=TV_C_RTN
=TV_C_RTN
69A8
69B8
69A8
69D7
Can tie the following rails to GND:
Leave GFX_VID<3..0> and GFX_VR_EN as NC.
Tie VCC_AXG and VCC_AXG_NCTF to GND.
Tie VCCA_DPLLA and VCCA_DPLLB to VCC (VCore).
Tie DPLL_REF_CLK and DPLL_REF_SSCLK to GND.
Can also tie CRT_DDC_*, L_CTRL_*, L_DDC_*, SDVO_CTRL_* and
Follow instructions for LVDS and CRT & TV-Out Disable above.
Internal Graphics Disable
and filtered at all times!
NOTE: Must keep VDDC_TVDAC powered
VCCD_CRT, VCCD_QDAC and VCC_SYNC.
VCCA_CRT_DAC, VCCA_DAC_BG, VCCA_TVx_DAC,
Tie DPLL_REF_CLK* and DPLL_REF_SSCLK* to VCC (VCore).
Internal Graphics Disable
and filtered at all times!
NOTE: Must keep VDDC_TVDAC powered
IN
IN
CLKREQ*
NC1
NC8
CL_CLK
CL_PWROK
CL_RST*
RSVD6
THERMTRIP*
PM_BM_BUSY*
RSVD4
RSVD3
RSVD7
SM_CKE1
SM_CK0*
SM_CKE0
SM_ODT0
SM_ODT2
SM_RCOMP
SM_RCOMP*
SM_VREF0
SM_VREF1
SM_RCOMP_VOL
SM_CS1*
SM_CS0*
RSVD14
RSVD11
RSVD10
RSVD9
RSVD5
RSVD8
RSVD2
DPLL_REF_CLK*
DPLL_REF_SSCLK
PEG_CLK
DMI_RXN1
DMI_RXN0
DMI_RXN3
DMI_RXN2
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_TXN0
DMI_RXP3
DMI_TXN2
DMI_TXN1
DMI_TXP0
DMI_TXN3
DMI_TXP1
DMI_TXP2
DMI_TXP3
PEG_CLK*
RSVD12
CL_DATA
CL_VREF
SDVO_CTRL_CLK
SDVO_CTRL_DATA
ICH_SYNC*
TEST1
TEST2
GFX_VID0
GFX_VID1
GFX_VID2
GFX_VR_EN
GFX_VID3
RSVD20
RSVD21
RSVD24
RSVD25
RSVD27
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD41
RSVD42
RSVD40
RSVD43
RSVD44
RSVD45
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG16
CFG15
CFG14
CFG17
CFG18
CFG19
CFG20
PM_DPRSTP*
PM_EXT_TS0*
PWROK
PM_EXT_TS1*
RSTIN*
DPRSLPVR
NC2
NC4
NC3
NC5
NC7
NC6
NC10
NC9
NC12
NC11
NC13
NC14
NC15
NC16
DPLL_REF_CLK
SM_RCOMP_VOH
SM_ODT3
SM_ODT1
RSVD13
SM_CS2*
SM_CS3*
SM_CK3
SM_CK4
SM_CK4*
SM_CKE3
RSVD1
SM_CKE4
DPLL_REF_SSCLK*
SM_CK3*
SM_CK1*
SM_CK1
SM_CK0
SA_MA14
RSVD22
RSVD23
RSVD26
SB_MA14
SM_CK2
SM_CK2*
SM_CK5
SM_CK5*
(2 OF 10)
RSVD
DDR MUXING
CLK
CFG
DMI
PM
GRAPHICS VID
ME
MISC
NC
OUT
OUT
OUT
OUT
OUT
BI
BI
IN
OUT
BI
BI
OUT
OUT
IN
IN
OUT
OUT
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
BI
OUT
BI
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
Clk used for PEG and DMI
NB_CFG<3>
High = DMIx4
NB CFG<8:0> used for debug access
IPU
NB_CFG<4>
NB_CFG<5>
DMI x2 Select
NOTE: GMCH CL_PWROK input must be PWRGD signal for
PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M,
If ME/AMT is not used, short CL_PWROK to PWROK.
PP1V05_S0M, PP0V9_S3M and PP0V9_S0M.
NB_CFG<18>
NB_CFG<15>
FSB Dynamic
ODT
NB_CFG<17>
NB_CFG<14>
NB_CFG<16>
NB_CFG<11>
NB_CFG<12>
NB_CFG<13>
DMI Lane
Reversal
SDVO/PCIe x1
Concurrent
NB_CFG<20>
NB_CFG<19>
00 = RESERVED
or PCIe x16
11 = Normal Operation
High = Reversed
Low = Only SDVO
NB_CFG<13:12>
High = Both active
Low = Normal
01 = XOR Mode Enabled
10 = All-Z Mode Enabled
High = Enabled
Low = Disabled
See Below
See Below
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Lane Reversal
PCIe Graphics
NB_CFG<9>
NB_CFG<10>
Low = Reversed
High = Normal
RESERVED
RESERVED
RESERVED
NB_CFG<7>
NB_CFG<6>
RESERVED
IPU
IPD
IPD
IPD
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
NB_CFG<8>
Low = DMIx2
RESERVED
RESERVED
IPU
IPU
NB CFG<13:12> require ICT access
IPU
27D1
20A4
10V
0.1uF
20%
CERM
402
2
1
C1616
10V
0.1uF
20%
CERM
402
2
1
C1615
OMIT
FCBGA
CRESTLINE
N20
R32
A37
AW4
AR49
BL31
BK31
BK14
BL15
BE16
BJ14
BJ15
BH18
BE13
BG16
BK16
BG20
BG37
BD39
AY32
BE29
BD24
BC23
AW23
AV23
AW25
BA25
BG23
BF23
BA23
BB23
AW30
AV29
K36
H35
BE24
BJ29
J12
AN13
AM12
AR13
AR12
C34
B34
B36
B37
A35
C44
N35
B44
D47
C48
BK20
AW20
BH39
R35
BJ18
BK18
BH20
BF19
BK22
BJ20
B51
H10
P37
D20
AM37
AL36
AM36
AR37
P36
AV20
AW49
J36
L36
L39
G41
K45
K44
BJ1
BK1
BL2
BL3
BL49
BL50
BK50
BK51
BK2
A49
A50
B50
C51
A5
E1
BJ51
G40
E36
B39
C38
A39
E35
G36
H47
H48
C42
B42
AM43
AM39
AJ42
AJ47
AM44
AM40
AJ41
AJ46
AN45
AN41
AJ39
AM47
AN46
AN42
AJ38
AN47
G39
AM50
AN49
AT43
AK50
AM49
C20
J20
G23
N23
F23
C23
C21
L35
N24
N33
L32
M24
M20
K23
E20
E23
J23
L23
R24
N27
P27
U1400
21B6 60C6
21B6 60C6
21B6 60C6
21B6 60C6
8B2
24C3 74A3
24C3 74A3
8B2
24C3 74A3
68A6
68A6
28B4
24B5
5%
1/16W
MF-LF
20K
402
2
1
R1691
5%
1/16W
MF-LF
0
402
2
1
R1690
24C359D870B3
8B2
44B8
1/16W
5%
MF-LF
10K
402
2
1
R1631
402
CERM
16V
10%
0.01UF
2
1
C1625
20%
CERM1
6.3V
2.2UF
603
2
1
C1624
402
1/16W
1%
MF-LF
1K
2
1
R1624
3.01K
MF-LF
1/16W
1%
402
2
1
R1622
20%
2.2UF
CERM1
6.3V
603
2
1
C1622
402
CERM
16V
10%
0.01UF
2
1
C1623
MF-LF
1%
1/16W
402
1K
2
1
R1620
1%
1/16W
MF-LF
392
402
2
1
R1641
1%
1K
1/16W
MF-LF
402
2
1
R1640
0.1uF
CERM
10V
20%
402
2
1
C1640
NBCFG_DMI_X2
1/16W
MF-LF
3.9K
5%
402
2
1
R1655
NBCFG_PEG_REVERSE
3.9K
MF-LF
1/16W
5%
402
2
1
R1659
MF-LF
5%
1/16W
3.9K
NBCFG_DYN_ODT_DISABLE
402
2
1
R1666
NBCFG_DMI_REVERSE
5%
1/16W
MF-LF
3.9K
402
2
1
R1669
NBCFG_SDVO_AND_PCIE
3.9K
MF-LF
1/16W
5%
402
2
1
R1670
60C6
30C432C672D3
31C432A572B3
29C870B3
29B870B3
29B870B3
8A6
8A6
8A6
8A6
15D7
24D5
8A6
402
MF-LF
1/16W
5%
0
21
R1600
9C6
22C245B370B3
8B2
44B8
9B2
22C459C770B3
27B559C7
30D4 72D3
31A4 72B3
31D4 72B3
30A4 72D3
30D4 72D3
31A4 72B3
31D4 72B3
30A4 72D3
30C6 32D6 72D3
30C4 32D6 72D3
31C6 32D6 72B3
30B4 32D6 72D3
31C4 32D5 72B3
30B6 32D6 72D3
31B4 32D6 72B3
31B6 32D6 72B3
30B4 32D6 72D3
30B6 32D6 72D3
31B4 32D6 72B3
31B6 32D6 72B3
402
20
1%
1/16W
MF-LF
2
1
R1610
402
20
MF-LF
1%
1/16W
2
1
R1611
20A5
29C3 75B3
29C3 75B3
8B2
8B2
8B2
8B2
23D2 71D3
23D2 71D3
23D2 71D3
23D2 71D3
23D2 71D3
23D2 71D3
23D2 71D3
23D2 71D3
23D2 71D3
23D2 71D3
23D2 71D3
23D2 71D3
23D2 71D3
23D2 71D3
23D2 71D3
23D2 71D3
10K
5%
1/16W
MF-LF
402
2
1
R1630
NB Misc Interfaces
SYNC_DATE=10/30/2006
SYNC_MASTER=T9_MLB
16
106
H
051-7559
GFX_VID<4>
DMI_N2S_P<0>
DMI_N2S_P<2>
CLINK_NB_CLK
CLINK_NB_DATA
=NB_CLINK_MPWROK
CLINK_NB_RESET_L
SDVO_CTRLCLK
TP_NB_RSVD<42>
TP_NB_RSVD<41>
TP_NB_RSVD<43>
NB_BSEL<1>
NB_CFG<3>
NB_CFG<9>
TP_NB_CFG<12>
TP_NB_CFG<15>
NB_CFG<16>
DMI_N2S_N<3>
DMI_N2S_P<1>
DMI_N2S_P<3>
GFX_VID<1>
=GFX_VR_EN
GFX_VID<3>
TP_LVDS_A_DATAP3
TP_NB_RSVD<34>
MEM_B_A<14>
TP_NB_RSVD<27>
TP_NB_RSVD<26>
TP_NB_RSVD<25>
NB_BSEL<0>
NB_CFG<5>
MEM_CKE<4>
TP_NB_RSVD<1>
MEM_CLK_P<0>
MEM_CLK_N<4>
MEM_CLK_N<3>
MEM_CLK_P<4>
MEM_CLK_P<3>
TP_NB_RSVD<13>
TP_NB_NC<16>
TP_NB_NC<15>
TP_NB_NC<14>
TP_NB_NC<13>
TP_NB_NC<11>
TP_NB_NC<12>
TP_NB_NC<9>
TP_NB_NC<10>
TP_NB_NC<6>
TP_NB_NC<7>
TP_NB_NC<5>
TP_NB_NC<3>
TP_NB_NC<2>
PM_EXTTS_L<0>
NB_CFG<20>
NB_CFG<19>
TP_NB_CFG<18>
TP_NB_CFG<14>
TP_NB_CFG<10>
TP_NB_RSVD<23>
TP_NB_RSVD<22>
TP_NB_RSVD<21>
TP_NB_RSVD<20>
NB_TEST2
NB_TEST1
TP_NB_RSVD<2>
TP_NB_RSVD<8>
TP_NB_RSVD<9>
TP_NB_RSVD<10>
TP_NB_RSVD<11>
MEM_CS_L<0>
MEM_CS_L<1>
MEM_CKE<0>
MEM_CLK_N<1>
MEM_CLK_P<1>
MEM_CLK_N<0>
TP_NB_RSVD<7>
TP_NB_RSVD<3>
TP_NB_RSVD<4>
TP_NB_NC<8>
TP_NB_NC<1>
NB_CLK100M_PCIE_P
DMI_S2N_P<0>
DMI_N2S_N<0>
SDVO_CTRLDATA
NB_CLKREQ_L
NB_SB_SYNC_L
TP_MEM_CLKN2
TP_MEM_CLKP5
TP_MEM_CLKN5
PM_BMBUSY_L
CPU_DPRSTP_L
VR_PWRGOOD_DELAY
PM_THRMTRIP_L
MEM_CS_L<2>
MEM_ODT<2>
MEM_ODT<3>
MEM_CS_L<3>
MEM_ODT<0>
MEM_ODT<1>
TP_NB_RSVD<6>
TP_NB_RSVD<12>
TP_NB_NC<4>
DMI_S2N_P<3>
=PP0V9_S3M_MEM_NBVREFB
TP_NB_RSVD<5>
TP_NB_RSVD<24>
TP_MEM_CLKP2
TP_LVDS_A_DATAN3
TP_LVDS_B_DATAP3
MEM_A_A<14>
TP_NB_RSVD<35>
TP_NB_RSVD<36>
TP_LVDS_B_DATAN3
TP_NB_RSVD<45>
TP_NB_RSVD<14>
PM_DPRSLPVR
NB_RESET_L
PM_EXTTS_L<1>
NB_CFG<16>
=PP3V3_S0_NB_VCCHV
NB_CFG<19>
NB_CFG<20>
=PP3V3_S0_NB_VCCHV
TP_NB_CFG<11>
TP_NB_CFG<13>
=PP3V3_S0_NB_VCCHV
TP_NB_CFG<17>
PP1V25_S0M_NB_VCCAXD
NB_CLINK_VREF
NB_BSEL<2>
NB_CFG<6>
NB_CFG<7>
NB_CFG<8>
NB_CFG<5>
MEM_RCOMP_L
TP_NB_RSVD<44>
NB_CFG<4>
MEM_CKE<1>
MEM_CKE<3>
=PP0V9_S3M_MEM_NBVREFA
MEM_RCOMP_VOL
MEM_RCOMP
=PP1V8_S3M_MEM_NB
MEM_RCOMP_VOH
NB_CFG<9>
GFX_VID<0>
=NB_CLK96M_DOT_P
=NB_CLK96M_DOT_N
=NB_CLK100M_DPLLSS_P
=NB_CLK100M_DPLLSS_N
NB_CLK100M_PCIE_N
DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_N2S_N<1>
DMI_N2S_N<2>
GFX_VID<2>
21B7
21B7
20A8
20A8
21B7
31D2
18B3
18B3
20A8
30D2
15C7
15C7
18B3
20C8
15B7
15B7
15C7
20A6
17D7
15D7
15D7
8D6
15B6
15C7
15C7
8B4
8B4
8B4
8B4
8D6
8D6
8D6
15B6
7D4
15B6
15B6
7D4
7D4
18C3
74A3
7A4
15B6
=PP1V8_S3M_MEM_NB
=PP1V8_S3M_MEM_NB
31D2
17D7
10V
CERM
31B4 32D6 72B3
31B6 32D6 72B3
=PP0V9_S3M_MEM_NBVREFB
=PP0V9_S3M_MEM_NBVREFB
=PP0V9_S3M_MEM_NBVREFA
=PP0V9_S3M_MEM_NBVREFA
C1615
IN
Clk used for PEG and DMI
29C3 75B3
8B2
NB_CLK100M_PCIE_P
NB_CLK100M_PCIE_P
=NB_CLK96M_DOT_P
=NB_CLK96M_DOT_P
=NB_CLK96M_DOT_N
=NB_CLK96M_DOT_N
=NB_CLK100M_DPLLSS_P
=NB_CLK100M_DPLLSS_P
=NB_CLK100M_DPLLSS_N
=NB_CLK100M_DPLLSS_N
NB_CLK100M_PCIE_N
NB_CLK100M_PCIE_N
Clk used for PEG and DMI
NB_CLK100M_PCIE_P
NB_CLK100M_PCIE_P
=NB_CLK96M_DOT_N
=NB_CLK96M_DOT_N
=NB_CLK100M_DPLLSS_P
=NB_CLK100M_DPLLSS_P
=NB_CLK100M_DPLLSS_N
=NB_CLK100M_DPLLSS_N
NB_CLK100M_PCIE_N
NB_CLK100M_PCIE_N
DMI_S2N_N<0>
DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<2>
DMI_S2N_N<3>
DMI_S2N_N<3>
DMI_RXN1
DMI_RXN0
DMI_RXN3
DMI_RXN2
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_TXN0
DMI_RXP3
DMI_TXN1
DMI_TXN3
PEG_CLK*
CFG
DMI
IPU
IPU
AJ46
AN45
AN41
AJ38
AN47
DMI_S2N_P<0>
DMI_S2N_P<0>
DMI_S2N_N<3>
DMI_S2N_N<3>
DMI_S2N_P<1>
DMI_S2N_P<1>
CFG4
F23
C21
N24
CFG16
CFG17
CFG18
CFG19
CFG20
L35
N33
K23
E20
CFG6
CFG7
CFG10
CFG11
CFG12
CFG13
IPU
IPU
IPU
IPU
IPU
IPU
C20
J20
G23
TP_NB_CFG<15>
TP_NB_CFG<15>
NB_CFG<16>
NB_CFG<16>
NB_CFG<20>
NB_CFG<20>
NB_CFG<19>
NB_CFG<19>
TP_NB_CFG<18>
TP_NB_CFG<18>
TP_NB_CFG<14>
TP_NB_CFG<14>
PM_BMBUSY_L
PM_BMBUSY_L
CPU_DPRSTP_L
CPU_DPRSTP_L
VR_PWRGOOD_DELAY
VR_PWRGOOD_DELAY
TP_NB_CFG<17>
TP_NB_CFG<17>
NB_CFG<20>
NB_CFG<20>
NB_CFG<19>
NB_CFG<19>
TP_NB_CFG<18>
TP_NB_CFG<18>
TP_NB_CFG<17>
TP_NB_CFG<17>
IN
OUT
59D8
24D5
22C2
9B2
27B5
TP_NB_NC<1>
TP_NB_NC<1>
MF-LF
PM_EXTTS_L<1>
PM_EXTTS_L<1>
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
BI
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ4
SA_DQ6
SA_DQ14
SA_CAS*
SA_BS2
SA_DQ63
SA_DQ62
SA_DQ61
SA_DQ60
SA_DQ59
SA_DQ58
SA_DQ57
SA_DQ56
SA_DQ55
SA_DQ54
SA_DQ53
SA_DQ52
SA_DQ51
SA_DQ50
SA_DQ49
SA_DQ48
SA_DQ47
SA_DQ46
SA_DQ44
SA_DQ43
SA_DQ42
SA_DQ41
SA_DQ40
SA_DQ39
SA_DQ38
SA_DQ37
SA_DQ36
SA_DQ34
SA_DQ35
SA_DQ33
SA_DQ32
SA_DQ31
SA_DQ30
SA_DQ28
SA_DQ29
SA_DQ27
SA_DQ26
SA_DQ25
SA_DQ24
SA_DQ23
SA_DQ22
SA_DQ21
SA_DQ20
SA_DQ19
SA_DQ18
SA_DQ17
SA_DQ16
SA_DQ15
SA_DQ13
SA_DQ11
SA_DQ12
SA_DQ10
SA_DQ9
SA_DQ8
SA_DQ7
SA_DQ5
SA_DQ3
SA_BS1
SA_BS0
SA_DQ45
SA_DM0
SA_DM1
SA_DM3
SA_DM2
SA_DM5
SA_DM4
SA_DM7
SA_DM6
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_DQS1*
SA_DQS0*
SA_DQS2*
SA_DQS4*
SA_DQS3*
SA_DQS5*
SA_DQS6*
SA_DQS7*
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA9
SA_MA8
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_RAS*
SA_RCVEN*
SA_WE*
DDR SYSTEM MEMORY A
(4 OF 10)
SB_DQ2
SB_DQ1
SB_DQ5
SB_DM0
SB_DQ0
SB_DQ4
SB_DQ6
SB_DQ7
SB_CAS*
SB_BS2
SB_BS0
SB_BS1
SB_DQ63
SB_DQ62
SB_DQ59
SB_DQ58
SB_DQ56
SB_DQ55
SB_DQ54
SB_DQ53
SB_DQ52
SB_DQ51
SB_DQ50
SB_DQ49
SB_DQ48
SB_DQ47
SB_DQ45
SB_DQ46
SB_DQ44
SB_DQ43
SB_DQ42
SB_DQ41
SB_DQ40
SB_DQ39
SB_DQ38
SB_DQ37
SB_DQ36
SB_DQ34
SB_DQ35
SB_DQ33
SB_DQ32
SB_DQ31
SB_DQ30
SB_DQ28
SB_DQ29
SB_DQ27
SB_DQ26
SB_DQ25
SB_DQ24
SB_DQ23
SB_DQ22
SB_DQ21
SB_DQ20
SB_DQ19
SB_DQ18
SB_DQ17
SB_DQ16
SB_DQ15
SB_DQ14
SB_DQ13
SB_DQ11
SB_DQ12
SB_DQ10
SB_DQ9
SB_DQ8
SB_DQ3
SB_DQ57
SB_DQ61
SB_DQ60
SB_WE*
SB_RCVEN*
SB_RAS*
SB_MA13
SB_MA12
SB_MA11
SB_MA10
SB_MA8
SB_MA9
SB_MA7
SB_MA6
SB_MA5
SB_MA4
SB_MA3
SB_MA2
SB_MA1
SB_MA0
SB_DQS7*
SB_DQS6*
SB_DQS5*
SB_DQS3*
SB_DQS4*
SB_DQS2*
SB_DQS0*
SB_DQS1*
SB_DQS7
SB_DQS6
SB_DQS5
SB_DQS4
SB_DQS3
SB_DQS2
SB_DQS1
SB_DQS0
SB_DM6
SB_DM7
SB_DM4
SB_DM5
SB_DM2
SB_DM3
SB_DM1
(5 OF 10)
DDR SYSTEM MEMORY B
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
30A672D3
30C6 72C3
30B6 72C3
30B4 72C3
30A4 72C3
30A6 72C3
30A4 72C3
30A6 72C3
30B6 72C3
30B4 72C3
30C4 72C3
30A672D3
30C6 72C3
30D4 72C3
31A672B3
31A472B3
31A672B3
31A472B3
31A672B3
31A672B3
31A472B3
31A472B3
30A672D3 31A672B3
31A672B3
31A472B3
31A672B3
31A472B3
31A472B3
31B672B3
31A672B3
31A472B3
31A472B3
30A472D3
31B672B3
31A672B3
31B472B3
31B472B3
31A472B3
31A672B3
31B672B3
31B672B3
31B472B3
31B472B3
30A472D3
31B672B3
31C672B3
31C672B3
31B672B3
31B472B3
31B472B3
31C472B3
31C672B3
31C472B3
31C672B3
30A672D3
31C472B3
31C472B3
31C472B3
31C672B3
31C472B3
31C672B3
31C472B3
31C672B3
31C672B3
31C472B3
30A672D3
31D472B3
31D472B3
31D472B3
31D672B3
31D472B3
31D672B3
31D672B3
31D672B3
31D672B3
30A472D3
31D472B3
31D472B3
31D672B3
31D472B3
31D672B3
31D472B3
31D672B3
31B6 32A6 72B3
31B4 32A6 72B3
31B4 32A5 72B3
30A672D3
31C6 32A5 72B3
31B6 32B5 72B3
31C4 32A5 72B3
31C6 32B5 72B3
31C6 32B5 72B3
31C4 32B5 72B3
31B6 32B5 72B3
31C4 32B5 72B3
31B4 32B5 72B3
31B6 32B5 72B3
30A472D3
31B4 32B5 72B3
31B6 32B5 72B3
31B4 32B5 72B3
31A4 72A3
31A6 72A3
31C4 72A3
31B6 72A3
31B4 72A3
31C6 72A3
31D6 72A3
30A472D3
31A6 72A3
31A4 72A3
31D6 72A3
31B6 72A3
31A4 72A3
31C4 72A3
31D6 72A3
31C6 72A3
31A6 72A3
31D6 72A3
30A672D3
31A6 72B3
31A4 72A3
31C6 72B3
31B4 72B3
31C4 72B3
31D4 72B3
31D4 72B3
31B6 32A6 72B3
31C6 32A6 72B3
31B6 32A6 72B3
30A472D3
31B4 32A6 72B3
FCBGA
CRESTLINE
OMIT
BA19
AY20
BE18
BA28
BL28
BJ25
BJ27
BK28
BL24
BH28
BK27
BJ16
BG30
BE28
BC19
BD20
BJ19
AP2
AP3
BC1
BB2
BH7
BH6
BA16
BB16
BA37
BC37
BC41
BB43
BD47
BE48
AT47
AT46
BF48
BB45
AW47
AN11
AM9
AN9
AT9
AT42
AN10
AM8
AN3
AR9
AR8
AR5
BB7
AY6
AT7
AT5
AR45
AY7
BB5
BB9
BD7
AW9
BG10
AY9
BD8
BD10
BE10
AR41
BA11
BA13
AT11
AU15
AV11
AW11
AT13
AV13
AT38
AV38
AY46
AY41
AW41
AW36
AT39
AW40
AR40
BF40
BG40
BH45
BF44
BA45
BE40
BG42
BE44
AW43
BE45
BH49
BG50
BB47
BJ45
BG47
AW44
AR43
AN6
AY5
BG8
AW13
AW38
BD42
BD44
AT45
BL17
BF29
BK19
BB19
U1400
FCBGA
CRESTLINE
OMIT
BC17
AY18
AV16
BD37
AY28
BC28
BA29
BE25
BF25
AW17
BG25
BG13
BA39
BE37
BG17
BG28
BC18
AV3
AV2
BF2
BE2
BK7
BL7
BK12
BJ12
BK38
BK39
BL45
BK46
BC50
BD50
AU50
AT50
BB50
BA50
AV49
AT2
AU2
AY3
AY2
AV50
AT3
AR1
BB3
BA3
BJ2
BD3
BE4
BK3
BC2
BG1
AN50
BH5
BF4
BJ6
BJ8
BK10
BK9
BL5
BK5
BL9
BJ10
AN51
BG12
BC12
BE12
BC13
BC11
BK11
BE11
BK13
BK37
BL35
AW51
BJ40
BK41
BJ36
BJ37
BL41
BJ41
BK42
BK43
BK49
BK47
AW50
BL43
BJ43
BJ44
BJ50
BF49
BF50
AY49
BA51
BE50
BA49
AR51
AP49
AW2
BF3
BJ7
BH12
BL39
BK45
BD49
AR50
BE17
BG36
BG18
AY17
U1400
30B472D3
30A672D3
30B672D3
30B672D3
30B472D3
30B672D3
30B672D3
30D472D3
30B472D3
30B672D3
30B472D3
30B472D3
30B672D3
30B472D3
30C672D3
30C472D3
30D472D3
30C472D3
30A672D3
30C672D3
30C472D3
30C672D3
30D672D3
30C672D3
30C472D3
30C672D3
30C472D3
30C672D3
30C672D3
30A472D3
30C472D3
30C472D3
30D472D3
30D472D3
30D672D3
30D472D3
30D472D3
30D672D3
30D672D3
30D672D3
30A472D3
30D672D3
30D472D3
30D472D3
30D472D3
30D672D3
30D672D3
30D672D3
30B6 32C6 72D3
30B4 32C6 72D3
30C6 32C6 72D3
30A472D3
30B6 32B6 72D3
30D4 72C3
30B4 32C6 72D3
30B4 32B6 72D3
30B6 32B6 72D3
30C6 32C6 72D3
30C4 32C6 72D3
30B6 32C6 72D3
30C6 32C6 72D3
30A672D3
30C6 32C6 72D3
30C4 32C6 72D3
30C4 32C6 72D3
30B6 32C6 72D3
30B4 32C6 72D3
30B6 32C6 72D3
30B4 32C6 72D3
30B6 32C6 72D3
30B4 32C6 72D3
30D6 72C3
30A472D3
30D6 72C3
30C4 72C3
30C6 72C3
30B6 72C3
30B4 72C3
30A4 72C3
30A6 72C3
30D6 72C3
30D6 72C3
30C4 72C3
SYNC_DATE=10/30/2006
SYNC_MASTER=T9_MLB
NB DDR2 Interfaces
051-7559
H
106
17
MEM_A_DQ<35>
TP_MEM_A_RCVEN_L TP_MEM_B_RCVEN_L
MEM_B_DQ<39>
MEM_B_BS<0>
MEM_B_BS<1>
MEM_B_BS<2>
MEM_B_DM<0>
MEM_B_CAS_L
MEM_B_DM<1>
MEM_B_DM<2>
MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>
MEM_B_DQS_P<1>
MEM_B_DQS_P<0>
MEM_B_DQS_P<4>
MEM_B_DQS_P<3>
MEM_B_DQS_P<2>
MEM_B_DQS_P<6>
MEM_B_DQS_P<5>
MEM_B_DQS_N<1>
MEM_B_DQS_P<7>
MEM_B_DQS_N<0>
MEM_B_DQS_N<3>
MEM_B_DQS_N<2>
MEM_B_DQS_N<4>
MEM_B_DQS_N<6>
MEM_B_DQS_N<5>
MEM_B_DQS_N<7>
MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_RAS_L
MEM_B_A<13>
MEM_B_WE_L
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>
MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DQ<2>
MEM_A_DQ<4>
MEM_A_DQ<6>
MEM_A_CAS_L
MEM_A_BS<2>
MEM_A_DQ<8>
MEM_A_DQ<7>
MEM_A_DQ<5>
MEM_A_DQ<3>
MEM_A_BS<1>
MEM_A_BS<0>
MEM_A_DM<0>
MEM_A_DM<1>
MEM_A_DM<3>
MEM_A_DM<2>
MEM_A_DM<5>
MEM_A_DM<4>
MEM_A_DM<7>
MEM_A_DM<6>
MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<1>
MEM_A_DQS_N<0>
MEM_A_DQS_N<2>
MEM_A_DQS_N<4>
MEM_A_DQS_N<3>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>
MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_RAS_L
MEM_A_WE_L
MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>
SB_DM0
SB_DQS3
SB_DQS2
SB_DQS1
SB_DQS0
SB_DM6
SB_DM7
SB_DM4
SB_DM5
SB_DM2
SB_DM3
BK46
BD50
AT50
AR50
BE17
MEM_B_BS<0>
MEM_B_BS<0>
MEM_B_BS<1>
MEM_B_BS<1>
MEM_B_BS<2>
MEM_B_BS<2>
MEM_B_DM<0>
MEM_B_DM<0>
MEM_B_CAS_L
MEM_B_CAS_L
MEM_B_DM<1>
MEM_B_DM<1>
MEM_B_DM<2>
MEM_B_DM<2>
MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<6>
MEM_B_DM<7>
MEM_B_DM<7>
MEM_B_DQS_P<1>
MEM_B_DQS_P<1>
MEM_B_DQS_P<0>
MEM_B_DQS_P<0>
MEM_B_DQS_P<3>
MEM_B_DQS_P<2>
MEM_B_DQS_P<2>
SB_DQ23
SB_DQ22
SB_DQ21
SB_DQ20
SB_DQ19
SB_DQ18
SB_DQ17
SB_DQ16
SB_DQ15
SB_DQ14
SB_DQ13
SB_DQ12
SB_DQS5
SB_DQS4
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_DQ28
SB_DQ27
SB_DQ26
SB_DQ25
SB_DQ24
SB_DQ23
BJ36
BJ37
BL41
BK49
BK47
MEM_B_DQ<22>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<23>
MEM_B_DQ<24>
BI
BI
BI
31C6
MEM_B_DQ<21>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<35>
BI
BI
BI
OUT
OUT
OUT
72B3
31A4
31A6
31B6
72B3
72B3
72B3
31B6
31B4
31C4
72B3
30C6 32C6 72D3
30C4 32C6 72D3
30B6 32C6 72D3
30C6 32C6 72D3
30C6 32C6 72D3
30C4 32C6 72D3
30C4 32C6 72D3
30B6 32C6 72D3
30B4 32C6 72D3
30B6 32C6 72D3
30B4 32C6 72D3
30B6 32C6 72D3
30B4 32C6 72D3
MEM_B_DQ<33>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<38>
TP_MEM_A_RCVEN_L
TP_MEM_A_RCVEN_L
MEM_A_A<6>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<7>
MEM_A_A<9>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<8>
MEM_A_A<10>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<13>
MEM_A_RAS_L
MEM_A_RAS_L
OUT
OUT
OUT
30B4 32B6 72D3
AY20
TP_MEM_A_RCVEN_L
TP_MEM_A_RCVEN_L
MEM_A_RAS_L
MEM_A_RAS_L
MEM_A_WE_L
MEM_A_WE_L
MEM_A_WE_L
MEM_A_WE_L
SA_DQ54
AR5
SA_DQ62
SA_DQ61
SA_DQ60
SA_DQ59
SA_DQ58
SA_DQ57
AN11
AM9
AM8
剩余75页未读,继续阅读
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