SoiSeek：全中文IC搜索引擎与THS8134 Datasheet

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"THS8134中文datasheet" THS8134是一款高性能的模拟数字转换器，主要用于视频信号处理。这款器件是三通道10位数模转换器(DAC)，设计能够以至少80百万样本每秒(MSPS)的速度运行，非常适合高速数字视频应用。它可以直接驱动一个双重终端的75欧姆负载，输出标准的视频电平，确保在视频系统中的无缝集成。 THS8134提供了多种输入模式，适应不同的视频格式。它可以支持3×10位4:4:4、2×10位4:2:2或1×10位4:2:2的配置，这些配置与国际电信联盟(ITU)的BT.656标准兼容，用于YPbPr/GBR的YUV分量视频信号的复用。这种灵活性使得THS8134适用于各种高清视频和广播系统。此外，THS8134还集成了同步信号的生成功能，可以产生双电平(EIA)或三电平(SMPTE)的同步信号，同步信号与视频信号的比例为7:3。这在处理视频流时确保了精确的定时和同步，增强了系统的稳定性。该器件的一个独特特性是其集成的同步-on-green (SOG)功能，它可以将同步信号插入到绿色亮度信号中，或者同步-on-all-channels，这对于在处理彩色视频信号时保持高质量的图像至关重要。SOG技术有助于减少干扰，提高视频信号的清晰度和色彩保真度。 THS8134的datasheet可在Soiseek这个全球首个全中文IC专业搜索引擎上找到，方便中国用户快速查找和下载中文版的技术资料。Soiseek提供的所有IC数据手册的中文译本仅供参考，版权归属于原始发布厂商。尽管Soiseek尽力提供准确的翻译，但对可能存在的翻译错误不承担责任，用户应以原始英文 datasheet 为准。同时，Soiseek强调，其提供的PDF版本数据手册同样来源于原始发布厂商，所有版权归属厂商。用户在使用THS8134或其他任何IC时，应确保遵循原版数据手册的内容，以确保正确和安全的操作。对于任何反馈、建议或问题，用户可以通过Soiseek的联系方式进行沟通。

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SLVS204C − APRIL 1999 − REVISED SEPTEMBER 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

(continued)

device configuration

Input data to the device can be supplied from a 3x10b GBR/YPbPr input port. If the device is configured to take

data from all three channels, the data is clocked in at each rising edge of CLK. All three DACs operate at the

full clock speed of CLK.

device configuration (continued)

In the case of 4:2:2 sampled data (for YPbPr) the device can be fed over either a 2x10 bit or 1x10 bit multiplexed

input port. An internal demultiplexer will route input samples to the appropriate DAC: Y at the rate of CLK, Pb

and Pr each at rate of one-half CLK.

According to ITU-BT.656 the sample sequence is Pb-Y-Pr over a 1x10 bit interface (Y-port). The sample

sequence starts at the first rising edge of CLK after BLANK

has been taken high (inactive). In this case the

frequency of CLK is two times the Y conversion speed and four times the conversion speed of both Pr and Pb.

With a 2x10 bit input interface, both the Y-port and the Pr-port are sampled on every CLK rising edge. The Pr-port

carries the sample sequence Pb-Pr. The sample sequence starts at the first rising edge of CLK after BLANK

has been taken high (inactive). In this case the frequency of CLK is equal to the conversion speed of Y and 2x

the conversion speed of both Pr and Pb.

The device’s operation mode is set by the M1 and M2 mode selection terminals, according to Table 1. The

operation mode also determines the blanking level, as explained below in the sync/blanking generation

sections.

Table 1. THS8133 Configuration

M1 M2_INT CONFIGURATION DESCRIPTION

L L GBR

3x10b−4:4:4

GBR mode 4:4:4. Data clocked in on each rising edge of CLK from G, B, and R input channels. For the

definition of the analog output levels during blanking, see note 1.

L H YPbPr

3x10b−4:4:4

YPbPr mode 4:4:4. Data clocked in on each rising edge of CLK from Y, Pb and Pr input channels. (see

Note 1). For the definition of the analog output levels during blanking, see note 1.

H L YPbPr

2x10b−4:2:2

YPbPr mode 4:2:2 2x10 bit. Data clocked in on each rising edge of CLK from Y & Pr input channels. A

sample sequence of Pb−Pr−... should be applied to the Pr port. At the first rising edge of CLK after

BLANK is taken high, Pb should be present on this port. For the definition of the analog output levels

during blanking, see note 1.

H H YPbPr

1x10b−4:2:2

YPbPr mode 4:2:2 1x10 bit (ITU-BT.656 compliant). Data clocked in on each rising edge of CLK from

Y input channel. For the definition of the analog output levels during blanking, see note 1.

NOTE 1: In all device versions, the blanking level on the AGY channel output corresponds to input code 0 of the DAC.

S In the THS8133CPHP and the THS8133ACPHP versions, the blanking level on the ABPb and ARPr channel outputs corresponds to

the 512 input code of the DAC, when sync is inserted on all three channels (INS3_INT=H) and to the 0 input code of the DAC, when

sync is only inserted on the Y channel (INS3_INT=L)

S In the THS8133BCPHP version, the blanking level on the ABPb and ARPr channel outputs corresponds to the 512 input code of the

DAC irrespective if sync is inserted on all three channels (INS3_INT=H), or if sync is inserted only on the Y channel (INS3_INT=L)

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