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首页PowerPC P2020芯片参考手册:QorIQ集成处理器
“P2020RM.pdf”是PowerPC P2020芯片的参考手册,主要关注这款双Power Architecture® e500v2处理器核的集成处理器,适用于网络、无线基础设施和电信应用。手册包含了对芯片的概述、应用实例、架构细节以及各种接口和控制器的详细描述。
P2020 QorIQ 集成处理器是Freescale Semiconductor生产的一款高性能芯片。该芯片的核心特性包括:
1. **概述**:提供了芯片的基本信息,包括功能块图,关键性能参数和芯片级特性。它强调了P2020在处理LTE和WiMax基带应用以及线路卡控制平面应用时的高效能。
2. **e500v2核心和内存单元**:e500v2是处理器的核心,是Power Architecture家族的一员,它提供高性能计算能力,并与内存单元协同工作,确保数据的快速存取。
3. **e500一致性模块(ECM)和地址映射**:ECM确保多核间的内存一致性,而地址映射定义了芯片内各个组件的内存访问权限和范围。
4. **集成安全引擎(SEC)**:提供高级安全功能,如加密和解密,保护系统免受恶意攻击。
5. **增强型三速以太网控制器**:支持高速网络连接,可以处理不同速度的以太网协议。
6. **USB 2.0**:提供通用串行总线接口,支持高速数据传输,广泛应用于外设连接。
7. **增强型安全数字主机控制器**:增强了对SD卡和其他数字媒体设备的安全管理。
8. **增强型串行外围接口(eSPI)**:用于与低功耗设备通信,如传感器和微控制器。
9. **DDR SDRAM控制器**:管理与DDR内存的交互,确保数据存取的高效和稳定。
10. **高速I/O接口**:包括PCI Express接口、串行RapidIO接口、SGMII(简化千兆位媒体独立接口)和高速接口复用。这些接口允许芯片与其他高性能设备如显卡、网络适配器等进行高速数据交换。
11. **可编程中断控制器**:管理来自不同源的中断请求,优化系统响应时间。
P2020芯片的设计考虑了多种应用需求,提供了强大的处理能力,丰富的接口选项和高级的安全特性,使其成为电信和网络基础设施领域的理想选择。手册详细介绍了每个组件的功能和操作,为开发者提供了全面的技术参考。
Section number Title Page
9.3.57 Processor core 1 current task priority register (PIC_CTPR_CPU1)..........................................................450
9.3.58 Processor core 1 who am I register (PIC_WHOAMI_CPU1)...................................................................451
9.3.59 Processor core 1 interrupt acknowledge register (PIC_IACK_CPU1)......................................................452
9.3.60 Processor core 1 end of interrupt register (PIC_EOI_CPU1)....................................................................453
9.4 Functional description...................................................................................................................................................453
9.4.1 Programming model considerations...........................................................................................................453
9.4.1.1 Global registers......................................................................................................................453
9.4.1.2 Global timer registers.............................................................................................................454
9.4.1.3 IRQ_OUT_B and critical interrupt summary registers..........................................................454
9.4.1.4 Performance monitor mask registers (PMMRs)....................................................................455
9.4.1.5 Message registers...................................................................................................................455
9.4.1.6 Shared message signaled registers.........................................................................................455
9.4.1.7 Interrupt source configuration registers.................................................................................455
9.4.1.8 Per-CPU (private access) registers.........................................................................................457
9.4.2 Flow of interrupt control............................................................................................................................459
9.4.2.1 Interrupts routed to cint or IRQ_OUT_B...............................................................................459
9.4.2.2 Interrupts routed to int............................................................................................................460
9.4.2.2.1 Interrupt source priority..................................................................................462
9.4.2.2.2 Interrupt acknowledge....................................................................................462
9.4.2.2.3 Spurious vector generation.............................................................................463
9.4.2.2.4 Nesting of interrupts.......................................................................................463
9.4.3 Interprocessor interrupts............................................................................................................................464
9.4.4 Message interrupts.....................................................................................................................................464
9.4.5 Shared message signaled interrupts...........................................................................................................464
9.4.6 PCI Express INTx/IRQn sharing...............................................................................................................465
9.4.7 Global timers..............................................................................................................................................466
9.4.8 Resets.........................................................................................................................................................467
9.4.9 Resetting the PIC.......................................................................................................................................467
9.4.9.1 Processor core initialization...................................................................................................467
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Section number Title Page
9.5 Initialization/application information...........................................................................................................................467
9.5.1 Programming guidelines............................................................................................................................468
9.5.1.1 PIC registers...........................................................................................................................468
9.5.1.2 Changing interrupt source configuration...............................................................................469
Chapter 10
I2C Interfaces
10.1 Overview.......................................................................................................................................................................471
10.2 Introduction to I2C........................................................................................................................................................471
10.2.1 What is the I2C module?............................................................................................................................471
10.2.2 I2C module block diagram.........................................................................................................................472
10.2.3 Features .....................................................................................................................................................472
10.2.4 Advantages of the I2C bus.........................................................................................................................473
10.2.5 Modes of operation....................................................................................................................................473
10.2.6 I2C-specific conditions..............................................................................................................................473
10.3 I2C external signal descriptions....................................................................................................................................474
10.3.1 Signal overview..........................................................................................................................................474
10.3.2 Detailed signal descriptions.......................................................................................................................474
10.4 I2C memory map/register definition.............................................................................................................................475
10.4.1 I2C address register (I2Cx_I2CADR)........................................................................................................476
10.4.2 I2C frequency divider register (I2Cx_I2CFDR)........................................................................................477
10.4.3 I2C control register (I2Cx_I2CCR)............................................................................................................479
10.4.4 I2C status register (I2Cx_I2CSR)..............................................................................................................480
10.4.5 I2C data register (I2Cx_I2CDR)................................................................................................................481
10.4.6 I2C digital filter sampling rate register (I2Cx_I2CDFSRR)......................................................................482
10.5 Functional description...................................................................................................................................................482
10.5.1 Transaction protocol..................................................................................................................................482
10.5.1.1 START condition...................................................................................................................483
10.5.1.2 Slave address transmission.....................................................................................................483
10.5.1.3 Repeated START condition...................................................................................................484
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Section number Title Page
10.5.1.4 STOP condition......................................................................................................................485
10.5.1.5 Protocol implementation details.............................................................................................485
10.5.1.5.1 Transaction monitoring-implementation details.............................................485
10.5.1.5.2 Control transfer-implementation details.........................................................485
10.5.1.6 Address compare-implementation details..............................................................................486
10.5.2 Arbitration procedure.................................................................................................................................487
10.5.2.1 Arbitration control..................................................................................................................487
10.5.3 Handshaking...............................................................................................................................................488
10.5.4 Clock control..............................................................................................................................................488
10.5.4.1 Clock synchronization............................................................................................................488
10.5.4.2 Input synchronization and digital filter..................................................................................489
10.5.4.2.1 Input signal synchronization...........................................................................489
10.5.4.2.2 Filtering of SCL and SDA lines......................................................................489
10.5.4.3 Clock stretching.....................................................................................................................489
10.5.5 Boot sequencer mode.................................................................................................................................490
10.5.5.1 EEPROM calling address.......................................................................................................491
10.5.5.2 EEPROM data format............................................................................................................491
10.6 Initialization/application information...........................................................................................................................494
10.6.1 Initialization sequence................................................................................................................................494
10.6.2 Generation of START................................................................................................................................495
10.6.3 Post-transfer software response.................................................................................................................495
10.6.4 Generation of STOP...................................................................................................................................496
10.6.5 Generation of repeated START.................................................................................................................496
10.6.6 Generation of SCL when SDA low............................................................................................................496
10.6.7 Slave mode interrupt service routine.........................................................................................................497
10.6.7.1 Slave transmitter and received acknowledge.........................................................................497
10.6.7.2 Loss of arbitration and forcing of slave mode.......................................................................497
10.6.8 Interrupt service routine flowchart.............................................................................................................498
P2020 QorIQ Integrated Processor Reference Manual, Rev. 2, 12/2012
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Section number Title Page
Chapter 11
DUART
11.1 Introduction...................................................................................................................................................................501
11.1.1 Overview....................................................................................................................................................501
11.1.1.1 Features..................................................................................................................................502
11.1.1.2 Modes of operation................................................................................................................503
11.2 DUART external signal descriptions............................................................................................................................503
11.3 DUART memory map/register definition.....................................................................................................................504
11.3.1 Receiver Buffer Registers (DUART_URBRn)..........................................................................................506
11.3.2 Transmitter Holding Registers (DUART_UTHRn)...................................................................................506
11.3.3 Divisor Least Significant Byte Registers (DUART_UDLBn)...................................................................507
11.3.4 Divisor Most Significant Byte Registers (DUART_UDMBn)..................................................................508
11.3.5 Interrupt Enable Register (DUART_UIERn)............................................................................................509
11.3.6 Interrupt ID Registers (DUART_UIIRn)...................................................................................................510
11.3.7 FIFO Control Registers (DUART_UFCRn)..............................................................................................511
11.3.8 Alternate Function Registers (DUART_UAFRn)......................................................................................513
11.3.9 Line Control Registers (DUART_ULCRn)...............................................................................................513
11.3.10 Modem Control Registers (DUART_UMCRn).........................................................................................515
11.3.11 Line Status Registers (DUART_ULSRn)..................................................................................................516
11.3.12 Modem Status Registers (DUART_UMSRn)............................................................................................517
11.3.13 Scratch Registers (DUART_USCRn)........................................................................................................518
11.3.14 DMA Status Registers (DUART_UDSRn)................................................................................................518
11.4 Functional description...................................................................................................................................................520
11.4.1 Serial interface...........................................................................................................................................520
11.4.1.1 START bit..............................................................................................................................521
11.4.1.2 Data transfer...........................................................................................................................521
11.4.1.3 Parity bit.................................................................................................................................522
11.4.1.4 STOP bit.................................................................................................................................522
11.4.2 Baud-rate generator logic...........................................................................................................................522
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Section number Title Page
11.4.3 Local loopback mode.................................................................................................................................523
11.4.4 Errors..........................................................................................................................................................523
11.4.4.1 Framing error.........................................................................................................................523
11.4.4.2 Parity error.............................................................................................................................524
11.4.4.3 Overrun error..........................................................................................................................524
11.4.5 FIFO mode.................................................................................................................................................524
11.4.5.1 FIFO interrupts.......................................................................................................................524
11.4.5.2 DMA mode select..................................................................................................................525
11.4.5.3 Interrupt control logic............................................................................................................525
11.5 DUART initialization/application information.............................................................................................................526
Chapter 12
Enhanced local bus controller (eLBC)
12.1 eLBC introduction........................................................................................................................................................527
12.1.1 Overview....................................................................................................................................................528
12.1.2 Features......................................................................................................................................................529
12.1.3 Modes of operation....................................................................................................................................530
12.1.3.1 eLBC bus clock and clock ratios............................................................................................530
12.1.3.2 Source ID debug mode...........................................................................................................531
12.2 eLBC external signal descriptions................................................................................................................................531
12.3 Enhanced Local Bus Controller (eLBC) Memory Map................................................................................................534
12.3.1 Base register 0 (eLBC_BR0).....................................................................................................................538
12.3.2 Options register 0 layout for GPCM Mode (eLBC_ORg0).......................................................................540
12.3.3 Options register 0 layout for FCM Mode (eLBC_ORf0)..........................................................................543
12.3.4 Options register 0 layout for UPM Mode (eLBC_ORu0)..........................................................................547
12.3.5 Base register n (eLBC_BRn).....................................................................................................................551
12.3.6 Options register n layout for GPCM Mode (eLBC_ORgn).......................................................................552
12.3.7 Options register n layout for FCM Mode (eLBC_ORfn)..........................................................................556
12.3.8 Options register n layout for UPM Mode (eLBC_ORun)..........................................................................560
12.3.9 UPM address register (eLBC_MAR).........................................................................................................562
P2020 QorIQ Integrated Processor Reference Manual, Rev. 2, 12/2012
20 Freescale Semiconductor, Inc.
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