ATmega32U2：低功耗USB微控制器规格详解

需积分: 9 189 浏览量更新于2024-07-15 收藏 4.36MB PDF 举报

"ATmega32U2是一款基于增强型RISC架构的低功耗CMOS 8位微控制器，具备ISP闪存和USB控制器功能。它适用于需要高效能、低能耗处理和USB接口的嵌入式应用。" ATmega32U2是Atmel公司推出的微控制器，该芯片的核心是8位的AVR增强型RISC架构，其设计旨在提供高处理性能和低功耗。RISC（Reduced Instruction Set Computer）架构以其精简指令集和高效的执行速度而闻名，ATmega32U2拥有125条强大的指令，其中大部分指令能在单个时钟周期内完成，使得处理器在16MHz工作频率下可达到16 MIPS（百万指令每秒）的吞吐量。这款微控制器配备了8K/16K/32K字节的ISP（In-System Programming）闪存，允许在系统编程，即无需额外设备即可更新程序代码。此外，还有512/512/1024字节的EEPROM（电可擦可编程只读存储器）和512/512/1024字节的内部SRAM（静态随机访问内存），满足数据存储需求。闪存和EEPROM具有一定的写入/擦除次数限制，分别为10,000次和100,000次，同时保证在特定温度下的数据保留时间，分别是20年（85°C）和100年（25°C）。 ATmega32U2的一个显著特性是内置了USB 2.0全速设备模块，完全符合USB规范2.0标准，支持48MHz的锁相环（PLL）以实现全速总线操作，数据传输速率可达12Mbit/s。芯片内有176字节的独立USB数据收发RAM（DPRAM），用于端点内存分配。端点0用于控制传输，大小从8到64字节不等，此外还提供了4个可编程端点，支持IN或OUT方向，以及批量、中断和同步传输类型。在安全性和保护方面，ATmega32U2支持编程锁功能，确保软件安全。在系统编程可以通过芯片上的引导程序硬件激活，在复位后进行。此外，还有真正的读写同时操作，允许在程序执行过程中进行数据写入和读取，而不会影响正常运行。 ATmega32U2是一款功能强大的微控制器，适合需要高效能、低功耗以及USB连接能力的嵌入式设计。其丰富的内存配置、强大的处理性能以及集成的USB功能使其成为许多物联网、消费电子和工业控制应用的理想选择。

7799D–AVR–11/10

ATmega8U2/16U2/32U2

7. AVR Memories

This section describes the different memories in the ATmega8U2/16U2/32U2. The AVR archi-

tecture has two main memory spaces, the Data Memory and the Program Memory space. In

addition, the ATmega8U2/16U2/32U2 features an EEPROM Memory for data storage. All three

memory spaces are linear and regular.

7.1 In-System Reprogrammable Flash Program Memory

The ATmega8U2/16U2/32U2 contains 8K/16K/32K bytes On-chip In-System Reprogrammable

Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash

is organized as 4K x 16, 8K x 16. For software security, the Flash Program memory space is

divided into two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 100,000 write/erase cycles. The

ATmega8U2/16U2/32U2 Program Counter (PC) is 16 bits wide, thus addressing the

8K/16K/32K program memory locations. The operation of Boot Program section and associated

Boot Lock bits for software protection are described in detail in “Memory Programming” on page

246. “Memory Programming” on page 246 contains a detailed description on Flash data serial

downloading using the SPI pins or the debugWIRE interface.

Constant tables can be allocated within the entire program memory address space (see the LPM

– Load Program Memory instruction description and ELPM - Extended Load Program Memory

instruction description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-

ing” on page 12.

7799D–AVR–11/10

ATmega8U2/16U2/32U2

For a detailed description of SPI, debugWIRE and Parallel data downloading to the EEPROM,

see page 259, page 244, and page 250 respectively.

7.3.1 EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 7-2 on page 22. A self-timing function,

however, lets the user software detect when the next byte can be written. If the user code con-

tains instructions that write the EEPROM, some precautions must be taken. In heavily filtered

power supplies, V

is likely to rise or fall slowly on power-up/down. This causes the device for

some period of time to run at a voltage lower than specified as minimum for the clock frequency

used. See “Preventing EEPROM Corruption” on page 19. for details on how to avoid problems in

these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed.

7.3.2 Preventing EEPROM Corruption

During periods of low V

CC,

the EEPROM data can be corrupted because the supply voltage is

too low for the CPU and the EEPROM to operate properly. These issues are the same as for

board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First,

a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec-

ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can

be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal

BOD does not match the needed detection level, an external low V

reset Protection circuit can

be used. If a reset occurs while a write operation is in progress, the write operation will be com-

pleted provided that the power supply voltage is sufficient.

7.4 I/O Memory

The I/O space definition of the ATmega8U2/16U2/32U2 is shown in “Register Summary” on

page 288.

All ATmega8U2/16U2/32U2 I/Os and peripherals are placed in the I/O space. All I/O locations

may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between

the 32 general purpose working registers and the I/O space. I/O Registers within the address

range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these regis-

ters, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to

the instruction set section for more details. When using the I/O specific commands IN and OUT,

the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space

using LD and ST instructions, 0x20 must be added to these addresses. The

ATmega8U2/16U2/32U2 is a complex microcontroller with more peripheral units than can be

supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the

7799D–AVR–11/10

ATmega8U2/16U2/32U2

Extended I/O space from 0x60 - 0x1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD

instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most

other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore

be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-

isters 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

7.4.1 General Purpose I/O Registers

The ATmega8U2/16U2/32U2 contains three General Purpose I/O Registers. These registers

can be used for storing any information, and they are particularly useful for storing global vari-

ables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F

are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

7.5 Register Description

7.5.1 EEARH and EEARL – The EEPROM Address Register

• Bits 15:12 – Res: Reserved Bits

These bits are reserved and will always read as zero.

• Bits 11:0 – EEAR[8:0]: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the

512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and

512. The initial value of EEAR is undefined. A proper value must be written before the EEPROM

may be accessed.

7.5.2 EEDR – The EEPROM Data Register

• Bits 7:0 – EEDR[7:0]: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to the

EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the

EEDR contains the data read out from the EEPROM at the address given by EEAR.

Bit 1514131211 10 9 8

0x22 (0x42) – – – – EEAR11 EEAR10 EEAR9 EEAR8 EEARH

0x21 (0x41) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

7654 3 2 10

Read/Write R R R R R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 X X X X

XXXXX X XX

Bit 76543210

0x20 (0x40) MSB LSB EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

剩余308页未读，继续阅读

fox0329

粉丝: 2
资源: 7

ATmega32U2：低功耗USB微控制器规格详解

ATmega32中文资料

mini_CNC:基于ATMega32u2的迷你数控钻床的AVR代码

ATmega32中文手册

APM板bootloader烧写Atmega2560的bootloader 烧写Atmega32U2的bootloader

BEAR-MK3S-32u2-firmware:适用于3DXFAB BEAR MK3S的ATmega 32u2固件

usb2812:用于 WS2812 LED 的 ATMega32u2 USB 驱动程序

ATMEGA8U2原理图

ATMEGA1281规格书

atmega16u2-Mega2560固件

对Atmega16U2固件写入1

最新资源