MPC8378EEC：PowerQUICC II Pro处理器详解

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"MPC8378EEC.pdf" 本文档介绍了Freescale Semiconductor的MPC8378EEC PowerQUICC II Pro处理器的关键特性，它是一款高效能、低功耗、高度集成的主机处理器，适用于各种打印和成像、消费电子以及工业应用。该处理器可作为打印系统中的主CPU和I/O处理器、网络交换机和线路卡、无线局域网（WLAN）、网络接入服务器（NAS）、虚拟私有网络路由器、智能网络接口卡（iNIC）以及工业控制器的理想选择。 MPC8378E处理器扩展了PowerQUICC系列，提供了更高的CPU性能，增加了更多功能，并实现了更快的接口，同时满足了市场时间、价格、功耗和封装尺寸的需求。它搭载了e300c4核心，内置32KB的L1指令和数据缓存以及片上内存管理单元（MMU），提升了处理效率和响应速度。在I/O方面，MPC8378E提供两个增强型的三速10/100/1000Mbps以太网接口，支持DDR1和DDR2 SDRAM，这允许高速的数据传输和高效的内存管理。此外，处理器还包括多种外设接口，如串行外围接口（SPI）、通用异步收发传输器（UART）、并行接口、通用输入输出（GPIO）等，以满足不同应用领域的连接需求。在功耗管理上，MPC8378E设计了节能模式，能够在不牺牲性能的情况下降低功耗，适合需要长时间运行的设备。其低功耗特性使得它在电池供电或电源受限的环境中表现出色。此外，该处理器还支持实时操作系统（RTOS）和嵌入式Linux等操作系统，为开发者提供了丰富的软件开发环境。硬件安全特性，如加密引擎和安全内存区域，增强了系统的安全性和数据保护，使其在网络安全应用中成为可靠的选择。 MPC8378EEC是针对多种嵌入式应用而设计的一款高性能处理器，通过其强大的处理能力、丰富的接口选项和优化的能耗管理，能够满足从家用电器到企业级设备的各种需求。其在设计时充分考虑了成本效益、快速上市和低功耗，使其成为业界一个极具竞争力的解决方案。

MPC8378E PowerQUICC

™

II Pro Processor Hardware Specifications, Rev. 2

16 Freescale Semiconductor

DDR1 and DDR2 SDRAM

6 DDR1 and DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the

MPC8378E. Note that DDR1 SDRAM is GV

(typ) = 2.5 V and DDR2 SDRAM is GV

(typ) = 1.8 V.

6.1 DDR1 and DDR2 SDRAM DC Electrical Characteristics

Table 12 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the

device when GV

(typ) = 1.8 V.

Table 13 provides the DDR2 capacitance when GV

(typ) = 1.8 V.

Table 12. DDR2 SDRAM DC Electrical Characteristics for GV

(typ) = 1.8 V

Parameter Symbol Min Max Unit Notes

I/O supply voltage GV

1.71 1.89 V 1

I/O reference voltage MV

REF

0.49 × GV

0.51 × GV

V2, 5

I/O termination voltage V

REF

–0.04 MV

REF

+0.04 V 3

Input high voltage V

REF

+ 0.140 GV

+0.3 V —

Input low voltage V

–0.3 MV

REF

– 0.140 V —

Output leakage current I

–40 40 μA4

Output high current (V

OUT

=1.40V) I

–13.4 — mA —

Output low current (V

OUT

=0.3V) I

13.4 — mA —

Note:

is expected to be within 50 mV of the DRAM GV

at all times.

REF

is expected to be equal to 0.5 × GV

, and to track GV

DC variations as measured at the receiver. Peak-to-peak

noise on MV

REF

may not exceed ±2% of the DC value.

is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MV

REF

. This rail should track variations in the DC level of MV

REF

Output leakage is measured with all outputs disabled, 0 V ≤ V

OUT

≤ GV

See AN3665,

MPC837xE Design Checklist

, for proper DDR termination.

Table 13. DDR2 SDRAM Capacitance for GV

(typ) = 1.8 V

Parameter Symbol Min Max Unit Notes

Input/output capacitance: DQ, DQS, DQS

68pF1

Delta input/output capacitance: DQ, DQS, DQS

DIO

—0.5pF1

Note:

This parameter is sampled. GV

= 1.8 V ± 0.090 V, f = 1 MHz, T

=25°C, V

OUT

= GV

/2, V

OUT

(peak-to-peak) = 0.2 V.

MPC8378E PowerQUICC

™

II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor 17

DDR1 and DDR2 SDRAM

Table 14 provides the recommended operating conditions for the DDR SDRAM component(s) when

(typ) = 2.5 V.

Table 15 provides the DDR capacitance when GV

(typ) = 2.5 V.

Table 16 provides the current draw characteristics for MV

REF

Table 14. DDR SDRAM DC Electrical Characteristics for GV

(typ) = 2.5 V

Parameter Symbol Min Max Unit Notes

I/O supply voltage GV

2.375 2.625 V 1

I/O reference voltage MV

REF

0.49 × GV

0.51 × GV

V2, 5

I/O termination voltage V

REF

– 0.04 MV

REF

+ 0.04 V 3

Input high voltage V

REF

+ 0.18 GV

+ 0.3 V —

Input low voltage V

–0.3 MV

REF

– 0.18 V —

Output leakage current I

–40 40 μA4

Output high current (V

OUT

= 1.9 V) I

–15.2 — mA —

Output low current (V

OUT

= 0.38 V) I

15.2 — mA —

Note:

is expected to be within 50 mV of the DRAM GV

at all times.

REF

is expected to be equal to 0.5 × GV

, and to track GV

DC variations as measured at the receiver. Peak-to-peak

noise on MV

REF

may not exceed ±2% of the DC value.

is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MV

REF

. This rail should track variations in the DC level of MV

REF

Output leakage is measured with all outputs disabled, 0 V ≤ V

OUT

≤ GV

See AN3665,

MPC837xE Design Checklist

, for proper DDR termination.

Table 15. DDR SDRAM Capacitance for GV

(typ) = 2.5 V

Parameter Symbol Min Max Unit Notes

Input/output capacitance: DQ, DQS C

68pF1

Delta input/output capacitance: DQ, DQS C

DIO

—0.5pF1

Note:

This parameter is sampled. GV

= 2.5 V ± 0.125 V, f = 1 MHz, T

= 25°C, V

OUT

=GV

/2, V

OUT

(peak-to-peak) = 0.2 V.

Table 16. Current Draw Characteristics for MV

REF

Parameter Symbol Min Typ Max Unit Note

Current draw for MV

REF

DDR1

DDR2

MVREF

—

250

150

600

400

μA1, 2

Note:

The voltage regulator for MV

REF

must be able to supply up to the stated maximum current.

This current is divided equally between MVREF1 and MVREF2, where half the current flows through each pin.

MPC8378E PowerQUICC

™

II Pro Processor Hardware Specifications, Rev. 2

20 Freescale Semiconductor

DDR1 and DDR2 SDRAM

The minimum frequency for DDR2 is 250 MHz data rate (125 MHz clock), 167 MHz data rate (83 MHz

clock) for DDR1.

Figure 4 shows the DDR1 and DDR2 SDRAM output timing for the MCK to MDQS skew measurement

DDKHMH

Figure 4. DDR Timing Diagram for t

DDKHMH

MDQS epilogue end t

DDKHME

–0.6 0.6 ns 6, 8

Note:

The symbols used for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state) (reference)(state)

for

inputs and t

(first two letters of functional block)(reference)(state)(signal)(state)

for outputs. Output hold time can be read as DDR timing

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,

DDKHAS

symbolizes DDR timing (DD) for the time t

MCK

memory clock reference (K) goes from the high (H) state until outputs

(A) are setup (S) or output valid time. Also, t

DDKLDX

symbolizes DDR timing (DD) for the time t

MCK

memory clock reference

(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.

ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ//MDM/MDQS.

Note that t

DDKHMH

follows the symbol conventions described in Note 1. For example, t

DDKHMH

describes the DDR timing (DD)

from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t

DDKHMH

can be modified through control

of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in

the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same

adjustment value. See the

MPC8379E PowerQUICC II Pro Host Processor Reference Manual

for a description and

understanding of the timing modifications enabled by use of these bits.

Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data MDQ, ECC, or

data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.

All outputs are referenced to the rising edge of MCK

at the pins of the microprocessor. Note that t

DDKHMP

follows the symbol

conventions described in Note 1.

Clock Control register is set to adjust the memory clocks by 1/2 the applied cycle.

See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.

Table 20. DDR1 and DDR2 SDRAM Output AC Timing Specifications (continued)

Parameter Symbol

Min Max Unit Notes

MDQS

MCK[n]

MCK

DDKHMHmax) = 0.6 ns

DDKHMH(min) = –0.6 ns

MDQS

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