GFSK解调器的低功耗多步相位域ADC设计

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"这篇研究论文详细介绍了用于GFSK解调器的一种新型7.9微安多步相位域ADC（Analog-to-Digital Converter），该技术显著提升了无线接收器的能效。在无线通信系统中，ADC是至关重要的组件，尤其是在低功耗应用如蓝牙低能量（Bluetooth Low Energy）协议定义的零中间频率（Zero-IF）GFSK接收器中。传统的幅度ADC在功率效率方面往往不足，而相位域ADC（Ph-ADC）因其能效优势而受到青睐。论文提出了一种创新的设计方案，采用专门设计的二进制编码方案和多步操作，大大减少了所需的电流元素和比较器数量。具体来说，新设计仅需52个电流元素和一个比较器，而文献中引用的设计则需要260个电流元素和8个比较器，这显著降低了硬件复杂性和功耗。文章还深入探讨了非理想因素，包括跨导误差和偏移误差对Ph-ADC性能的影响。作者进行了理论分析，并提出了优化策略来减少转换点错误，从而提高解调器的精度和稳定性。通过仿真结果，该数字密集型Ph-ADC在180纳米CMOS工艺下，仅从1.8伏电源消耗7.9微安的电流，显示出了极高的能效比。此外，论文还可能涵盖了Monte-Carlo模拟分析，这是评估电路性能统计分布和不确定性的常见方法。这有助于理解在实际制造过程中，由于工艺变化导致的性能变化，从而确保设计在各种条件下的鲁棒性。总体而言，这篇研究为GFSK解调器的低功耗设计提供了重要的理论依据和实用解决方案，对于推动无线通信技术特别是物联网(IoT)设备的电源效率提升具有重要意义。"

Different signals generated by the resistor bridge vary in

amplitude due to different times of operations, which

worsens differential nonlinearity of the Ph-ADC. (2) A

large amount of transconductance cells are required to

drive the resistor bridge, leading to much current con-

sumption. The total current consumption reported in [10]is

290 lA. (3) Critical matching is needed in the resistor

bridge. Larger resistors are neces sary for better matching,

which leads to higher chip area.

In [12], a current mirror based combiner for Ph-ADC is

proposed, as shown in Fig. 2(b). The phase quantization is

fulﬁlled by different sizes of current mirrors. This structure

avoids the amplitude variation problem in resistor bridge

combiners. However, there is a trade-off between power

and matching, which still comes as a design challenge.

Larger current mirror sizes face fewer matching problems,

yet may increase chip area and introduce more parasitic

effects, limiting circuit speed in a power-constrained

design.

In both resistor bridge based Ph-ADCs and current

mirror based Ph-ADCs, 8 thermometer coded output bits

[Fig. 3(a)] are gener ated simultaneously for each input

sample, which is similar to the amplitude ﬂash ADCs. A

large number of resistor/current elements and comparators

are required inevitably. For example, the current mirror

based Ph-ADC in [12] employs 260 current elements and 8

comparators, which results in excessive power consump-

tion. A charge redistribution Ph-ADC based on an IQ-as-

sisted conversion algorithm is proposed in [13, 14], which

avoids the use of combiner. Power is reduced compared to

[10] and [12]. However, 4 comparators are utilized in

[13, 14], which still leaves room for optimization.

To achieve a good trade-off between quantization speed/

accuracy and circuit complexity, a multi-step Ph-ADC is

proposed in this work. The multi-step conversion is similar

to the idea in successive-approximation (SAR) ADC with

good power/speed efﬁciency [16]. With multi-step

conversion, the proposed Ph-ADC requires only 52 current

elements and 1 comparator.

2.2 Operation principle of proposed Ph-ADC

architecture

In the proposed Ph-ADC, the complex plane is equally

divided into 16 sections. The phase resolution is 22.5 and

the trip points on the ADC transfer curve are given by

= n  22.5 (0 B n B 15), as shown in Fig. 3(b). The

22.5 resolution is enough to detect 90 phase rotation

according to the BLE protocol.

In conventional Ph-ADCs, 8 b its thermometer codes are

adopted for quantization, as shown in Fig. 3(a). 8 bits

thermometer codes require 8 parallel comparators or one

comparator which operates 8 times serially. To reduce the

number of comparing operation, 4 bits binary-weighted

codes are proposed in this paper, which is shown in

Fig. 3(b). The bit deﬁnition is given in Table 1, where

m and k are integers.

By deﬁnition, tan U

= Q/I = (V

- V

)/(V

), where U

is the phase of the IF sign al.

1. The trip points where B

alters between 0 and 1 are

= 90 or 270. At these trip points, V

= 0, and bit B

can be determined by comparing

with V

IN,

as shown in Fig. 4(a).

2. The trip points where B

alters between 0 and 1 are

= 0 or 180. At these trip points, V

- V

= 0,

and bit B

can be determined by comparing V

with

, as shown in Fig. 4 (b).

3. The trip points where B

alters between 0 and 1 are

= (2 m ? 1)  45. At these trip points, (V

)/(V

- V

) = tan (2m ? 1)  45 = 1or-1,

depending on the values of B

and B

. Thus, bit B

can

be determined by comparing the absolute value of

1111

1110

1101

1100

0100

0101

0110

0111

0011

0010

0001

0000 1000

1001

1010

1011

(a) (b)

Fig. 3 a Thermometer code in

conventional Ph-ADCs.

b Binary code in proposed SAR

Ph-ADC

Analog Integrated Circuits and Signal Processing (2018) 94:49–63 51

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