DIX4192：数字音频接口接收器与发送器

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"TI-DIX4192.pdf 是德州仪器(Texas Instruments, TI)发布的一份技术文档，主要介绍DIX4192这款数字音频接口接收器和发送器。该器件集成了数字音频接口的发送和接收功能，适用于各种音频应用。" DIX4192是一款高度集成的数字音频接口设备，它包含了数字音频接口发送器(Digital Interface Transmitter, DIT)和接收器(Digital Interface Receiver, DIR)。DIT支持最高216kHz的采样率，其输出采用差分线路驱动器和CMOS缓冲，确保高质量的音频传输。DIR部分则具备宽泛的锁相环(PLL)锁定范围，能处理20kHz到216kHz之间的各种采样率。它具有四个差分输入线路接收器和一个输入多路复用器，可以自动检测非PCM音频流，如DTSCD/LD和IEC 61937格式，同时具备音频CD Q通道子代码解码和数据缓冲功能。该器件提供低抖动恢复时钟输出，确保音频信号的稳定。用户可以选择通过SPI或I2C接口进行16位调光控制，访问片上寄存器和数据缓冲区。DIX4192还具有状态寄存器，能够生成标记条件和错误条件的中断，以及通道状态和用户数据的块大小数据缓冲区。此外，DIX4192有两个音频串行端口（Port A和Port B），支持外部信号处理器、数据转换器和逻辑的同步串行接口。这些端口可以在216kHz的采样率下进行主/从模式操作，兼容左对齐、右对齐和飞利浦I2S数据格式，并且能处理高达24位的音频数据字长。最后，DIX4192还包括四个通用数字输出，这些输出可以多功能配置，通过控制寄存器可以根据需求进行定制，使得该器件在音频系统设计中具有很高的灵活性和适应性。总体而言，DIX4192是音频设备设计中的关键组件，适用于需要高质量数字音频接口的各种应用，如家庭娱乐系统、专业音频设备和汽车音响系统等。

DIR_OUT

PORT_A_IN

PORT_B_IN

Audio Serial

Port A

Audio Serial

Port B

Digital

Interface

Receiver (DIR)

Digital

Interface

Transmitter

(DIT)

TX+

TX-

SDINA

SDOUTA

LRCKA

BCKA

SDINB

SDOUTB

LRCKB

BCKB

CPM

CS or A0

CCLK or SCL

CDIN or A1

CDOUT or SDA

INT

RST

Host

Interface

(SPI or I C)

and

General-

Purpose

Outputs

Master

Clock

Distribution

MCLK

RXCKI

From RXCKO

GPO1

GPO2

GPO3

GPO4

AESOUT

RXCKO

LOCK

RX2+

RX2-

RX3+

RX3-

RX4+

RX4-

RX1+

RX1-

BLS

SYNC

Control and Status

Registers

DIR C and U

Data Buffers

DIT C and U

Data Buffers

TI Device

Power

VDD18

DGND1

VDD33

DGND2

VIO

DGND3

VCC

AGND

BGND

Internally Tied

to Substrate

PORT A

PORT B

DIR

DIT

DIX4192

ZHCSG80F –FEBRUARY 2006–REVISED SEPTEMBER 2016

www.ti.com.cn

9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 RESET Operation

The DIX4192 includes an asynchronous active low reset input, RST (pin 24), which may be used to initialize the

internal logic at any time. The reset sequence forces all registers and buffers to their default settings. The reset

low pulse duration must be a minimum of 500 ns in length. The user must not attempt a write or read operation

using either the SPI or I

C port for at least 500 μs after the rising edge of RST. See Figure 6 for the reset timing

sequence of the DIX4192.

In addition to reset input, the RESET bit in control register 0x01 may be used to force an internal reset, whereby

all registers and buffers are forced to their default settings. Refer to Control Registers for details regarding the

RESET bit function.

Upon reset initialization, all functional blocks of the DIX4192 default to the power-down state, with the exception

of the SPI or I

C host interface and the corresponding control registers. The user may then program the DIX4192

to the desired configuration, and release the desired function blocks from the power-down state using the

corresponding bits in control register 0x01.

RST

500ns (min)

500 sm (min)

Write orRead

via

S IorP I C

DIX4192

www.ti.com.cn

ZHCSG80F –FEBRUARY 2006–REVISED SEPTEMBER 2016

Feature Description (continued)

Figure 6. Reset Sequence Timing

9.3.2 Master and Reference Clocks

The DIX4192 includes two clock inputs, MCLK (pin 25) and RXCKI (pin 13). The MCLK clock input is typically

used as the master clock source for the audio serial ports and/or the DIT. The MCLK may also be used as the

reference clock for the DIR. The RXCKI clock input is typically used for the DIR reference clock source, although

it may also be used as the master or reference clock source for the audio serial ports.

In addition to the MCLK and RXCKI clock sources, the DIR core recovers a master clock from the AES3-

encoded input data stream. This clock is suitable for use as a master or system clock source in many

applications. The recovered master clock output, RXCKO (pin 12), may be used as the master or reference clock

source for the audio serial ports and the DIT, as well as external audio devices.

The master clock frequency for the audio serial ports (Port A and Port B) depends on the Slave or Master mode

configuration of the port. In Slave mode, the ports do not require a master clock because the left/right word and

bit clocks are inputs, sourced from an external audio device serving as the serial bus timing master. In Master

mode, the serial ports derive the left/right word and bit clock outputs from the selected master clock source,

MCLK, RXCKI, or RXCKO. The left/right word clock rate is derived from the selected master clock source using

one of four clock divider settings (divide by 128, 256, 384, or 512). Refer to Audio Serial Port Operation for

additional details.

The DIT always requires a master clock source, which may be either the MCLK input, or the DIR recovered clock

output, RXCKO. Like the audio serial ports, the DIT output frame rate is derived from the selected master clock

using one of four clock divider settings (divide-by-128, -256, -384, or -512). Refer to Digital Interface Transmitter

(DIT) Operation for additional details.

The DIR reference clock may be any frequency that meets the PLL1 set-up requirements, described in Control

Registers. Typically, a common audio system clock rate, such as 11.2896 MHz, 12.288 MHz, 22.5792 MHz, or

24.576 MHz, may be used for this clock.

TI recommends that the clock sources for MCLK and RXCKI input be generated by low-jitter crystal oscillators for

optimal performance. In general, phase-locked loop (PLL) clock synthesizers must be avoided, unless they are

designed or specified for low clock jitter.

Master

Clock

Source

Master

Mo ed

Clock

Generation

Serial

Input

Serial

Output

MC KL

RXCKI

RXCKO

Audio Data

InternalClocks

OUTS[1:0] MU ET F T[1:M 0]

M/S DIV1:[ 0]CLK1:[ 0]

SDNI A (pin39)or SDINB(pin4 )6

LRCKA (pin3 )or8 LRCKB( i 47)p n

BCKA(pin37)orBCKB(pin48)

SDOUTA (pin40)or SDOUTB(pin45)

Daat

Source

PortA

PortB

DIR

DIX4192

ZHCSG80F –FEBRUARY 2006–REVISED SEPTEMBER 2016

www.ti.com.cn

Feature Description (continued)

9.3.3 Audio Serial Port Operation

The DIX4192 includes two audio serial ports, Port A and Port B. Both ports are 4-wire synchronous serial

interfaces, supporting simultaneous input and output operation. Because each port has only one pair of left or

right word and bit clocks, the input and output sampling rates are identical. A simplified block diagram is shown in

Figure 7.

The audio serial ports may be operated at sampling rates up to 216 kHz, and support audio data word lengths up

to 24 bits. Philips I

S, Left-Justified, and Right-Justified serial data formats are supported. Refer to Figure 8.

The left or right word clock (LRCKA or LRCKB) and the bit clock (BCKA or BCKB) may be configured for either

Master or Slave mode operation. In Master mode, these clocks are outputs, derived from the selected master

clock source using internal clock dividers. The master clock source may be 128, 256, 384, or 512 times the audio

input/output sampling rate, with the clock divider being selected using control register bits for each port. In Slave

mode the left or right word and bit clocks are inputs, and are sourced from an external audio device acting as the

serial bus master.

The LRCKA or LRCKB clocks operate at the input and output sampling rate, f

. The BCKA and BCKB clock rates

are fixed at 64 times the left or right word clock rate in Master mode. For Slave mode, the minimum BCKA and

BCKB clock rate is determined by the audio data word length multiplied by two, because there are two audio

data channels per left or right word clock period. For example, if the audio data word length is 24 bits, the bit

clock rate must be at least 48 times the left or right word clock rate, allowing one bit clock period for each data bit

in the serial bit stream.

Serial audio data is clocked into the port on the rising edge of the bit clock, while data is clocked out of the port

on the falling edge of the bit clock. Refer to the Audio Serial Ports section of the Electrical Characteristics table

for parametric information and Figure 1 for a timing diagram related to audio serial port operation.

The audio serial ports are configured using control registers 0x03 through 0x06. Refer to Control Registers for

descriptions of the control register bits.

Figure 7. Audio Serial Port Block Diagram

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