微处理器架构：实现视角

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"Processor Microarchitecture - An Implementation Perspective" 这本书——《Processor Microarchitecture - An Implementation Perspective》是计算机架构领域的一本重要著作，由Antonio González、Fernando Latorre和Grigorios Magklis共同撰写，于2011年出版。这本书与经典的《量化方法》相比，更注重于解释和展示现代微处理器架构中的技术实现，以更易于理解的方式让读者掌握处理器设计的核心概念。微处理器架构是计算机科学中的关键部分，它涉及到如何设计和构建高效的处理器，以执行指令并处理数据。本书涵盖了多个主题，旨在深入探讨计算机硬件组件的设计、分析、选择和互连，以满足功能、性能和成本目标。内容范围广泛，与ISCA（国际超级计算大会）、HPCA（高性能计算机架构会议）、MICRO和ASPLOS等顶级计算机架构会议的研究领域相吻合。书中的重点可能包括： 1. **指令集架构（ISA）**：讨论不同类型的指令集，如RISC（精简指令集）和CISC（复杂指令集），以及它们在处理器实现中的优缺点。 2. **处理器核心设计**：涵盖单核、多核和多线程处理器的设计，包括同步多线程（SMT）技术，以及核心间的通信机制。 3. **缓存系统**：讲解各级缓存（L1、L2、L3）的工作原理，以及缓存一致性问题，包括MESI协议和其他一致性协议。 4. **内存层次结构**：深入研究主存、虚拟内存、DDR内存等，以及内存访问延迟对性能的影响。 5. **并行处理**：介绍向量处理、多处理器系统、分布式共享内存（DSM）和事务性内存（Transactional Memory）的概念，以及它们在提高处理器性能中的应用。 6. **互连网络**：探讨芯片内的通信网络，如片上网络（On-Chip Networks），以及它们在多核处理器中的作用。 7. **存储系统**：强调内存系统的重要性，包括高速缓存层次、主存管理和虚拟内存系统的设计策略。 8. **故障容错**：讲解在计算机架构中实现容错的策略和技术，以确保系统的可靠性和稳定性。 9. **性能评估模型**：介绍如何通过模型来预测和分析处理器的性能，以及如何进行性能优化。通过阅读这本书，读者不仅可以了解微处理器架构的基本原理，还能获得实际设计和实现的洞察，这对于计算机工程和软件开发者来说是极其宝贵的。对于那些想要深入理解现代计算机内部工作原理的人来说，这本书无疑是一个宝贵的资源。

INTRODUCTION 5

remains in the reorder buffer until it commits. The goal of the reorder buffer is to store information

about the instruction that is useful for its execution but also for squashing it if necessary.

Memory operations are handled in a special manner. They need to compute the effective ad-

dress, which typically is done in the same way as an arithmetic instruction. However, besides access-

ing the data cache, they may need to check their potential dependences with other in-ﬂight memory

instructions. The load/store queue stores the requited information for this, and the associated logic

is responsible for determining when and in which order memory instructions are executed.

In an in-order processor, instructions ﬂow through these phases in the program order. This

means that if an instruction is stalled for some reason (e.g., an unavailable operand), younger in-

structions may not surpass it, so they may need to be stalled too.

In a superscalar processor, each one of the components described above has the capability of

processing multiple instructions at the same time. Besides, it is quite normal to add buffers between

some pipeline stages to decouple them and in this manner allow the processor to hide some of the

stalls due to different types of events such as cache misses, operands not ready, etc. These buffers are

quite common between fetch and decode, decode and rename and dispatch and issue.

1.3.1 Overview of the Pipeline

This section presents an overview of the main components of the pipeline. A detailed description of

them is presented in following chapters.

FIGURE 1.1: High-level block diagram of a microprocessor.

6 PROCESSOR MICROARCHITECTURE: AN IMPLEMENTATION PERSPECTIVE

The ﬁrst part of the pipeline is responsible for fetching instructions. The main components of

this part of the pipeline are (a) an instruction cache, where instructions are stored, and (b) a branch

predictor that determines the address of the next fetch operation.

The next part is the instruction decode. The main components of this part are decoders,

ROMs and ad-hoc circuitry, whose main objective is to identify the main attributes of the instruc-

tion such as type (e.g., control ﬂow) and resources that it will require (e.g., register ports, functional

units).

Afterward, the instructions ﬂow to the allocation phase, where the two main actions that

are performed are register renaming and dispatch. Register renaming entails changing the names of

the register operands with the purpose of removing all false dependences and therefore maximiz-

ing the instruction-level parallelism that the processor can exploit. This is done normally through

a set of tables that contain information about the current mapping of logical names to physical

ones and what names are not being used at this point in time, together with some logic to analyze

dependences among the multiple instructions being renamed simultaneously, since the destination

and source register of a producer-consumer pair has to be renamed in a consistent manner. The

instruction dispatch consists of reserving different resources that the instruction will use, including

entries in the reorder buffer, issue queue and load/store buffers. If resources are not available, the

corresponding instruction is stalled until some other instruction releases the required resources.

The next phase in the pipeline is devoted to instruction issue. Instructions sit in the issue

queue until the issue logic determines that their execution can start. For in-order processors, the

issue logic is relatively simple. It basically consists of a scoreboard that indicates which operands are

available and a simple logic that checks whether the instructions sitting at the head of the queue

have all their operands ready. For out-of-order processors, this logic is quite complex since it entails

analyzing all the instructions in the queue at every cycle to check for readiness of their operands and

availability of the resources that they will require for execution.

After being issued, instructions go to the execution part of the pipeline. Here there is a variety

of execution units for different types of operations, which normally include integer, ﬂoating-point

and logical operations. It is also quite common nowadays to include special units for SIMD opera-

tions (single instruction, multiple data, also referred to as vector operations). Another important

component of the execution pipeline is the bypass logic. It consists basically of wires that can move

results from one unit to the input of other units and the associated logic that determines whether

results should use the bypass instead of using the data coming from the register ﬁle. The design of

the bypass network is critical in most processors since wire delays do not scale at the same pace as

gate delays, so they have an important contribution to the cycle time of the processor.

Finally, instructions move to the commit phase. The main purpose of this part of the pipeline

is to give the appearance of sequential execution (i.e., same outcome) even though instructions are

Caches store recently accessed program data and instructions, in the hope that they will be needed

in the near future, based on the observation that program memory accesses exhibit signiﬁcant spa-

tial and temporal locality. By buffering such frequently accessed data in a small and fast structure,

the processor can give the illusion to the application that accesses to main memory are in the order

of a few cycles.

Data caches usually are organized in hierarchies of between 1 and 3 levels, so we can talk

about the ﬁrst-level cache, the second-level cache, etc. The lower the level, the closer to the proces-

sor the cache is located. Level 1 data caches usually have low associativity and store several tens of

kilobytes of data arranged in cache blocks of around 64 bytes each, and they can be accessed in a few

cycles (between 1 and 4, usually). Normally, processors have two ﬁrst-level caches, one for program

data (the data cache) and one for program instructions (the instruction cache). Second- and third-

level caches are usually between several hundreds of kilobytes and a few megabytes in size, have very

high associativity and take tens of cycles to access. These caches usually hold both program data and

instructions. Moreover, although each core in a multicore processor has its own (private) ﬁrst-level

caches, higher levels of the memory hierarchy are usually shared among multiple cores. In this sec-

tion, we will focus the discussion on ﬁrst-level data caches.

Normally, program data and instruction addresses are virtual addresses. Load and store instruc-

tions as well as the fetch engine must perform address translation (more on this later) to translate

the virtual addresses to physical addresses. The caches can be indexed with either virtual or physical

addresses. In the former case, the cache access can be initiated earlier, since the address translation

can be performed in parallel with the cache access. To deal with potential aliasing problems, the tags

are normally generated from the physical address.

Load and store instructions have to take several steps in order to access the data cache. First,

the virtual address of the memory access has to be calculated in the address generation unit (AGU),

as will be discussed in Chapter 7. In the case of stores, the store queue is updated with this address,

and in the case of loads, the store queue is checked for disambiguation (Chapter 6). When the dis-

ambiguation logic decides that a load can proceed (or when a store reaches its commit phase), the

data cache is accessed.

C H A P T E R 2

Caches

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