
Maxim > App Notes > A/D and D/A CONVERSION/SAMPLING CIRCUITS HIGH-SPEED SIGNAL PROCESSING
Keywords: integral nonlinearity, INL, differential nonlinearity, DNL, analogue-to-digital, analog-to-digital, high-
speed, high performance, data converters, ADCs, digital-to-analog, digital-to-analogue, converter, DACs
Sep 01, 2000
APPLICATION NOTE 283
INL/DNL Measurements for High-Speed Analog-to-Digital Converters
(ADCs)
Abstract: Although integral and differential nonlinearity may not be the most important parameters for high-
speed, high dynamic performance data converters, they gain significance when it comes to high-resolution
imaging applications. The following application note serves as a refresher course for their definitions and details
two different, yet commonly used techniques to measure INL and DNL in high-speed analog-to-digital
converters (ADCs).
Manufacturers have recently introduced high-performance analog-to-digital converters (ADCs) that feature
outstanding static and dynamic performance. You might ask, "How do they measure this performance, and what
equipment is used?" The following discussion should shed some light on techniques for testing two of the
accuracy parameters important for ADCs: integral nonlinearity (INL) and differential nonlinearity (DNL).
Although INL and DNL are not among the most important electrical characteristics that specify the high-
performance data converters used in communications and fast data-acquisition applications, they gain
significance in the higher-resolution imaging applications. However, unless you work with ADCs on a regular
basis, you can easily forget the exact definitions and importance of these parameters. The next section therefore
serves as a brief refresher course.
INL and DNL Definitions
DNL error is defined as the difference between an actual step width and the ideal value of 1LSB (see Figure 1a).
For an ideal ADC, in which the differential nonlinearity coincides with DNL = 0LSB, each analog step equals 1LSB
(1LSB = V
FSR
/2
N
, where V
FSR
is the full-scale range and N is the resolution of the ADC) and the transition values
are spaced exactly 1LSB apart. A DNL error specification of less than or equal to 1LSB guarantees a monotonic
transfer function with no missing codes. An ADC's monotonicity is guaranteed when its digital output increases
(or remains constant) with an increasing input signal, thereby avoiding sign changes in the slope of the transfer
curve. DNL is specified after the static gain error has been removed. It is defined as follows:
DNL = |[(V
D+1
- V
D
)/V
LSB-IDEAL
- 1] | , where 0 < D < 2
N
- 2.
V
D
is the physical value corresponding to the digital output code D, N is the ADC resolution, and V
LSB-IDEAL
is the
ideal spacing for two adjacent digital codes. By adding noise and spurious components beyond the effects of
quantization, higher values of DNL usually limit the ADC's performance in terms of signal-to-noise ratio (SNR)
and spurious-free dynamic range (SFDR).