STM32L476RG：低功耗超值ARM Cortex-M4微控制器

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STM32L476RG是一款高性能、低功耗的微控制器，基于Arm Cortex-M4架构，集成了浮点单元(FPU)和适应性实时加速器(ART Accelerator)，支持0等待状态执行，最高工作频率可达80MHz。该芯片的特点包括： 1. **电源管理**：它具有FlexPowerControl，可以在1.71V到3.6V的宽电压范围内工作，并能承受-40°C至85/105/125°C的温度范围，确保了在各种环境下的可靠运行。电池模式下功耗极低，仅300nA，足以供应RTC和32x32位备份寄存器。此外，提供了多种低功耗状态选项，如Shutdown模式（30nA，5个唤醒引脚）、Standby模式（120/420nA，5个唤醒引脚）、Stop 2模式（1.1/1.4μA）等。 2. **性能与能效**：在性能方面，STM32L476RG表现出色，1.25 DMIPS/MHz的性能和3.42 CoreMark/MHz的分数显示其强大的处理能力。在能效方面，通过ULPMark评估，它在典型应用中的CP分数达到294分，PP分数为106分，体现出出色的能源管理能力。 3. **时钟源选择**：芯片提供多个时钟源选项，包括4到48MHz晶体振荡器、32kHz LSE用于RTC、内部16MHz RC振荡器（精度±1%）以及自动校准的多速100kHz到48MHz振荡器（精度优于±0.25%）。还配置了3个PLL，分别用于系统时钟、USB、音频和ADC。 4. **丰富的I/O接口**：该设备拥有114个快速I/O端口，其中部分可以耐受5V电压，支持触摸传感器和LCD显示（8x40或4x44，配备升压转换器）。它还配备了多达24个电容式触控通道，以及16个定时器，包括高级电机控制定时器、通用定时器和低功耗定时器，以及两个看门狗和一个SysTick定时器。 5. **内存配置**：STM32L476RG内置1MB Flash（可进行读写操作，有代码保护功能），128KB SRAM（其中32KB带有硬件奇偶校验），以及外部内存接口支持多种存储类型。此外，还有Quad SPI内存接口。 6. **模拟外设**：包含3个12位高采样率ADC（最大16位，硬件过采样）、2个12位DAC输出通道、2个带内增益放大器的运算放大器和2个低功耗比较器。 7. **通信接口**：提供了USB OTG 2.0全速接口、两个串行音频接口(SAI)、多个I2C、USART和IrDA通信模块，支持多种标准协议。这款STM32L476RG微控制器因其全面的功能、低功耗特性及出色的性能，适用于对能源效率、处理能力和连接性有高要求的应用，如工业自动化、物联网(IoT)设备、消费电子和智能嵌入式系统。

Description STM32L476xx

16/270 DS10198 Rev 7

Random generator Yes

GPIOs

(2)

Wakeup pins

Nb of I/Os down to

1.08 V

114

109

Capacitive sensing

Number of channels

24 24 21 12 12 12

12-bit ADCs

Number of channels

12-bit DAC channels 2

Internal voltage

reference buffer

Yes No

Analog comparator 2

Operational amplifiers 2

Max. CPU frequency 80 MHz

Operating voltage (V

) 1.71 to 3.6 V

Operating voltage

DD12

)

1.05 to 1.32 V

Operating temperature

Ambient operating temperature: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C

Junction temperature: -40 to 105 °C / -40 to 125 °C / -40 to 130 °C

Packages

LQFP144

UFBGA144

UFBGA

132

LQFP100 WLCSP81 WLCSP72 LQFP64

1. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory

using the NE1 Chip Select.

2. In case external SMPS package type is used, 2 GPIO's are replaced by VDD12 pins to connect the SMPS power supplies

hence reducing the number of available GPIO's by 2.

Table 2. STM32L476xx family device features and peripheral counts (continued)

Peripheral

STM32

L476Zx

STM32

L476Qx

STM32

L476Vx

STM32

L476Mx

STM32

L476Jx

STM32

L476Rx

DS10198 Rev 7 17/270

STM32L476xx Description

Figure 1. STM32L476xx block diagram

Note: AF: alternate function on I/O pins.

MS31263V8

USB

OTG

Flash

up to

1 MB

Flexible static memory controller (FSMC):

SRAM, PSRAM, NOR Flash,

NAND Flash

GPIO PORT A

AHB/APB2

EXT IT. WKUP

114 AF

PA[15:0]

TIM1 / PWM

3 compl. channels (TIM1_CH[1:3]N),

4 channels (TIM1_CH[1:4]),

ETR, BKIN, BKIN2 as AF

USART1

RX, TX, CK,CTS,

RTS as AF

SPI1

MOSI, MISO,

SCK, NSS as AF

APB260 M Hz

APB1 30MHz

MOSI, MISO, SCK, NSS as AF

DAC1_OUT1

ITF

WWDG

RTC_TS

OSC32_IN

OSC32_OUT

smcard

IrDA

16b

SDIO / MMC

D[7:0]

CMD, CK as AF

VBAT = 1.55 to 3.6 V

SCL, SDA, SMBA as AF

JTAG & SW

ARM Cortex-M4

80 MHz

FPU

NVIC

ETM

MPU

DMA2

ART

ACCEL/

CACHE

CLK, NE[4:1], NL, NBL[1:0],

A[25:0], D[15:0], NOE, NWE,

NWAIT, NCE3, INT3 as AF

RNG

FIFO

@ VDDA

BOR

Supply

supervision

PVD, PVM

Int

reset

XTAL 32 kHz

MAN AGT

RTC

FCLK

Standby

interface

IWDG

@VBAT

@ VDD

@VDD

AWU

Reset & clock

control

PCLKx

Voltage

regulator

3.3 to 1.2 V

VDD

Power management

@ VDD

RTC_TAMPx

Backup register

AHB bus-matrix

TIM15

2 channels,

1 compl. channel, BKIN as AF

TIM6

TIM7

TIM2

TIM3

TIM4

TIM5

USART2

USART3

I2C1/SMBUS

D-BUS

FIFO

APB1 80 MHz (max)

SRAM 96 KB

SRAM 32 KB

I-BUS

S-BUS

DMA1

PB[15:0]

PC[15:0]

PD[15:0]

PE[15:0]

PF[15:0]

PG[15:0]

PH[1:0]

GPIO PORT B

GPIO PORT C

GPIO PORT D

GPIO PORT E

GPIO PORT F

GPIO PORT G

GPIO PORT H

TIM8 / PWM

16b

TIM16

16b

TIM17

16b

3 compl. channels (TIM1_CH[1:3]N),

4 channels (TIM1_CH[1:4]),

ETR, BKIN, BKIN2 as AF

1 channel,

1 compl. channel, BKIN as AF

1 channel,

1 compl. channel, BKIN as AF

DAC1_OUT2

16b

SCL, SDA, SMBA as AF

MOSI, MISO, SCK, NSS as AF

TX, RX as AF

RX, TX, CTS, RTS as AF

RX, TX, CK, CTS, RTS as AF

smcard

IrDA

smcard

IrDA

32b

16b

32b

4 channels, ETR as AF

AHB/APB1

OSC_IN

OSC_OUT

HCLKx

XTAL OSC

4- 16MHz

8 analog inputs common

to the 3 ADCs

VREF+

USAR T 2MBps

Temperature sensor

ADC1

ADC2

ADC3

ITF

@ VDDA

8 analog inputs common

to the ADC1 & 2

8 analog inputs for ADC3

SAI1

MCLK_A, SD_A, FS_A, SCK_A, EXTCLK

MCLK_B, SD_B, FS_B, SCK_B as AF

SAI2

MCLK_A, SD_A, FS_A, SCK_A, EXTCLK

MCLK_B, SD_B, FS_B, SCK_B as AF

DFSDM

SDCKIN[7:0], SDDATIN[7:0],

SDCKOUT,SDTRIG as AF

Touch sensing controller

8 Groups of

3 channels max as AF

VOUT, VINM, VINP

LCD 8x40

LPUART1

SWPMI1

LPTIM1

LPTIM2

SEGx, COMx as AF

RX, TX, CTS, RTS as AF

RX, TX, SUSPEND as AF

IN1, IN2, OUT, ETR as AF

IN1, OUT, ETR as AF

RC HSI

RC LSI

PLL 1&2&3

MSI

Quad SPI memory interface

BK1_IO[3:0]

CLK

NCS

@ VDDUSB

COMP1

INP, INM, OUT

COMP2

INP, INM, OUT

@ VDDA

RTC_OUT

FIFO

PHY

AHB1 80 MHz

CRC

I2C2/SMBUS

I2C3/SMBUS

bxCAN1

OpAmp1

SP3

SP2

UART5

UART4

LCD Booster

LCD

= 2.5V to 3.6V

APB2 80MHz

AHB2 80 MHz

OpAmp2

@VDDA

Firewall

VREF Buffer

@ VDDA

@ VDD

SCL, SDA, INTN, ID, VBUS, SOF

VDD = 1.71 to 3.6 V

VSS

VDDA, VSSA

VDD, VSS, NRST

VDDIO2, VDDUSB

VOUT, VINM, VINP

TRACECLK

TRACED[3:0]

NJTRST, JTDI,

JTCK/SWCLK

JTDO/SWD, JTDO

VDD12 = 1.05 to 1.32 V

(1)

VDD12

1. Only available when using external SMPS supply mode.

DAC1

Functional overview STM32L476xx

18/270 DS10198 Rev 7

3 Functional overview

3.1 Arm

Cortex

-M4 core with FPU

The Arm

Cortex

-M4 with FPU processor is the latest generation of Arm

processors for

embedded systems. It was developed to provide a low-cost platform that meets the needs of

MCU implementation, with a reduced pin count and low-power consumption, while

delivering outstanding computational performance and an advanced response to interrupts.

The Arm

Cortex

-M4 with FPU 32-bit RISC processor features exceptional code-

efficiency, delivering the high-performance expected from an Arm

core in the memory size

usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions which allow efficient signal processing and

complex algorithm execution.

Its single precision FPU speeds up software development by using metalanguage

development tools, while avoiding saturation.

With its embedded Arm

core, the STM32L476xx family is compatible with all Arm

tools

and software.

Figure 1 shows the general block diagram of the STM32L476xx family devices.

3.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-

standard Arm

Cortex

-M4 processors. It balances the inherent performance advantage of

the Arm

Cortex

-M4 over Flash memory technologies, which normally requires the

processor to wait for the Flash memory at higher frequencies.

To release the processor near 100 DMIPS performance at 80MHz, the accelerator

implements an instruction prefetch queue and branch cache, which increases program

execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the

performance achieved thanks to the ART accelerator is equivalent to 0 wait state program

execution from Flash memory at a CPU frequency up to 80 MHz.

3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to

prevent one task to accidentally corrupt the memory or resources used by any other active

task. This memory area is organized into up to 8 protected areas that can in turn be divided

up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4

gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be

protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-

time operating system). If a program accesses a memory location that is prohibited by the

MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can

dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

DS10198 Rev 7 19/270

STM32L476xx Functional overview

3.4 Embedded Flash memory

STM32L476xx devices feature up to 1 Mbyte of embedded Flash memory available for

storing programs and data. The Flash memory is divided into two banks allowing read-

while-write operations. This feature allows to perform a read operation from one bank while

an erase or program operation is performed to the other bank. The dual bank boot is also

supported. Each bank contains 256 pages of 2

Kbyte.

Flexible protections can be configured thanks to option bytes:

• Readout protection (RDP) to protect the whole memory. Three levels are available:

– Level 0: no readout protection

– Level 1: memory readout protection: the Flash memory cannot be read from or

written to if either debug features are connected, boot in RAM or bootloader is

selected

– Level 2: chip readout protection: debug features (Cortex-M4 JTAG and serial

wire), boot in RAM and bootloader selection are disabled (JTAG fuse). This

selection is irreversible.

• Write protection (WRP): the protected area is protected against erasing and

programming. Two areas per bank can be selected, with 2-Kbyte granularity.

• Proprietary code readout protection (PCROP): a part of the flash memory can be

protected against read and write from third parties. The protected area is execute-only:

it can only be reached by the STM32 CPU, as an instruction code, while all other

accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.

One area per bank can be selected, with 64-bit granularity. An additional option bit

(PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP

protection is changed from Level 1 to Level 0.

Table 3. Access status versus readout protection level and execution modes

Area

Protection

level

User execution

Debug, boot from RAM or boot

from system memory (loader)

Read Write Erase Read Write Erase

Main

memory

1 Yes Yes Yes No No No

2 Yes Yes Yes N/A N/A N/A

System

memory

1 Yes No No Yes No No

2 Yes No No N/A N/A N/A

Option

bytes

1 Yes Yes Yes Yes Yes Yes

2 Yes No No N/A N/A N/A

Backup

registers

1YesYesN/A

(1)

1. Erased when RDP change from Level 1 to Level 0.

No No N/A

(1)

2 Yes Yes N/A N/A N/A N/A

SRAM2

1 Yes Yes Yes

(1)

No No No

(1)

2 Yes Yes Yes N/A N/A N/A

Functional overview STM32L476xx

20/270 DS10198 Rev 7

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

• single error detection and correction

• double error detection.

• The address of the ECC fail can be read in the ECC register

3.5 Embedded SRAM

STM32L476xx devices feature up to 128 Kbyte of embedded SRAM. This SRAM is split into

two blocks:

• 96 Kbyte mapped at address 0x2000 0000 (SRAM1)

• 32 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).

This block is accessed through the ICode/DCode buses for maximum performance.

These 32 Kbyte SRAM can also be retained in Standby mode.

The SRAM2 can be write-protected with 1 Kbyte granularity.

The memory can be accessed in read/write at CPU clock speed with 0 wait states.

3.6 Firewall

The device embeds a Firewall which protects code sensitive and secure data from any

access performed by a code executed outside of the protected areas.

Each illegal access generates a reset which kills immediately the detected intrusion.

The Firewall main features are the following:

• Three segments can be protected and defined thanks to the Firewall registers:

– Code segment (located in Flash or SRAM1 if defined as executable protected

area)

– Non-volatile data segment (located in Flash)

– Volatile data segment (located in SRAM1)

• The start address and the length of each segments are configurable:

– Code segment: up to 1024 Kbyte with granularity of 256 bytes

– Non-volatile data segment: up to 1024 Kbyte with granularity of 256 bytes

– Volatile data segment: up to 96 Kbyte with a granularity of 64 bytes

• Specific mechanism implemented to open the Firewall to get access to the protected

areas (call gate entry sequence)

• Volatile data segment can be shared or not with the non-protected code

• Volatile data segment can be executed or not depending on the Firewall configuration

The Flash readout protection must be set to level 2 in order to reach the expected level of

protection.

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