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首页NXP i.MX6Q处理器参考手册概览
"i.MX6Q英文参考手册是NXP官方提供的一份详细技术文档,主要针对i.MX6系列的应用处理器,特别是i.MX6Dual和i.MX6Quad型号。这份手册包含了芯片的介绍、内存映射、中断与DMA事件、外部信号与引脚复用、熔丝映射以及外部存储器控制器等多个方面的内容,是进行i.MX6开发的重要参考资料。"
在本手册中,你可以了解到以下关键知识点:
1. **介绍**:手册首先介绍了文档的目的和目标应用领域,通常包括i.MX6系列处理器在消费电子、工业控制、汽车电子等领域的应用。同时,它列出了处理器的主要特性,比如高性能的Cortex-A9内核、多模式DDR控制器等,并提供了架构概述。
2. **内存映射**:这部分详细阐述了i.MX6处理器的内存系统结构,包括ARM平台的内存映射、DDR内存如何映射到MMDC(Multi-Mode DDR Controller)控制器端口,以及DMA(Direct Memory Access)内存映射,这对于理解和优化内存访问效率至关重要。
3. **中断和DMA事件**:中断系统是实时系统中的重要组成部分,手册详细解释了Cortex-A9内核支持的中断类型,并给出了SDMA(Simple Direct Memory Access)事件的映射,帮助开发者理解如何配置和管理中断及DMA传输。
4. **外部信号与引脚复用**:这部分介绍了处理器外部引脚的功能和配置,包括引脚的多功能性,如何根据需要复用这些引脚来连接不同的外设,这对于硬件设计者尤其有用。
5. **熔丝映射**:熔丝映射章节提供了芯片内部熔丝的布局和功能表,这些熔丝常用于配置芯片的某些特性或锁定特定功能,是定制化和安全性的关键部分。
6. **外部存储器控制器**:手册深入讲解了MMDC如何控制DDR内存,以及对Raw NAND闪存和EIM-PSRAM/NOR闪存控制器的概述,这些控制器负责与外部存储设备的通信,确保数据的稳定读写。
这份手册对于那些需要开发基于i.MX6系列处理器的硬件和软件工程师来说,是一份非常宝贵的资源,提供了全面的技术细节和配置指导,可以帮助他们有效地利用i.MX6的性能和特性。
Section number Title Page
49.4 External Signals............................................................................................................................................................ 4190
49.5 Functional Description..................................................................................................................................................4190
49.6 System Operation..........................................................................................................................................................4193
49.7 Control Memory Map/Register Definition................................................................................................................... 4195
Chapter 50
Power Management Unit (PMU)
50.1 Overview.......................................................................................................................................................................4253
50.2 Digital LDO Regulators................................................................................................................................................4255
50.3 Analog LDO Regulators............................................................................................................................................... 4256
50.4 USB LDO Regulator.....................................................................................................................................................4258
50.5 SNVS Regulator............................................................................................................................................................4258
50.6 Power Modes................................................................................................................................................................ 4258
50.7 PMU Memory Map/Register Definition.......................................................................................................................4259
Chapter 51
Pulse Width Modulation (PWM)
51.1 Overview.......................................................................................................................................................................4281
51.2 External Signals............................................................................................................................................................ 4282
51.3 Clocks........................................................................................................................................................................... 4283
51.4 Functional Description..................................................................................................................................................4284
51.5 Enable Sequence for the PWM.....................................................................................................................................4286
51.6 Disable Sequence for the PWM....................................................................................................................................4287
51.7 PWM Memory Map/Register Definition......................................................................................................................4287
Chapter 52
ROM Controller with Patch (ROMC)
52.1 Overview.......................................................................................................................................................................4297
52.2 Clocks........................................................................................................................................................................... 4299
52.3 Memory Map................................................................................................................................................................ 4299
52.4 Functional Description..................................................................................................................................................4300
52.5 ROMCP Memory Map/Register Definition..................................................................................................................4305
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16 NXP Semiconductors
Section number Title Page
Chapter 53
Serial Advanced Technology Attachment Controller (SATA)
53.1 Introduction...................................................................................................................................................................4313
53.2 Block Overview............................................................................................................................................................ 4314
53.3 Architecture...................................................................................................................................................................4317
53.4 Programming.................................................................................................................................................................4366
53.5 Software Manipulation of Port DMA........................................................................................................................... 4369
53.6 Register Descriptions....................................................................................................................................................4370
53.7 SATA Memory Map/Register Definition..................................................................................................................... 4371
Chapter 54
Serial Advanced Technology Attachment PHY (SATA PHY)
54.1 Overview.......................................................................................................................................................................4419
54.2 External Signals............................................................................................................................................................ 4425
54.3 Functional Description..................................................................................................................................................4425
54.4 Control Registers.......................................................................................................................................................... 4442
54.5 Timing and Specifications............................................................................................................................................ 4445
54.6 clock Memory Map/Register Definition.......................................................................................................................4470
54.7 lane0 Memory Map/Register Definition.......................................................................................................................4493
Chapter 55
Smart Direct Memory Access Controller (SDMA)
55.1 Overview.......................................................................................................................................................................4519
55.2 External Signals............................................................................................................................................................ 4523
55.3 Clocks........................................................................................................................................................................... 4523
55.4 Functional Description..................................................................................................................................................4523
55.5 Instruction Set...............................................................................................................................................................4637
55.6 Software Restrictions....................................................................................................................................................4693
55.7 Application Notes......................................................................................................................................................... 4694
55.8 Arm Platform Memory Map and Control Register Definitions....................................................................................4709
55.9 BP Memory Map and Control Register Definitions..................................................................................................... 4733
55.10 SDMA Internal (Core) Memory Map and Internal Register Definitions..................................................................... 4736
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Section number Title Page
55.11 SDMA Peripheral Registers..........................................................................................................................................4752
Chapter 56
System JTAG Controller (SJC)
56.1 Overview.......................................................................................................................................................................4753
56.2 External Signals............................................................................................................................................................ 4757
56.3 TAP Selection Block (TSB)..........................................................................................................................................4763
56.4 Boundary Scan Register (BSR) ................................................................................................................................... 4765
56.5 SJC Instruction Register (SJIR) ...................................................................................................................................4765
56.6 Security......................................................................................................................................................................... 4771
56.7 Functional Description..................................................................................................................................................4776
56.8 Initialization/Application Information..........................................................................................................................4777
56.9 SJC Memory Map/Register Definition.........................................................................................................................4778
Chapter 57
Secure Non-Volatile Storage (SNVS)
57.1 SNVS overview............................................................................................................................................................ 4791
57.2 External signals.............................................................................................................................................................4792
57.3 Clocks........................................................................................................................................................................... 4792
57.4 SNVS structure............................................................................................................................................................. 4793
57.5 SNVS_LP (low-power domain)....................................................................................................................................4796
57.6 SNVS reset and system powerup..................................................................................................................................4797
57.7 SNVS interrupts and alarms..........................................................................................................................................4799
57.8 Programming guidelines...............................................................................................................................................4800
57.9 SNVS Memory Map/Register Definition..................................................................................................................... 4801
Chapter 58
Shared Peripheral Bus Arbiter (SPBA)
58.1 Overview.......................................................................................................................................................................4827
58.2 Clocks........................................................................................................................................................................... 4830
58.3 Functional description...................................................................................................................................................4831
58.4 Resource ownership control..........................................................................................................................................4834
58.5 SPBA Memory Map/Register Definition......................................................................................................................4837
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Section number Title Page
Chapter 59
Sony/Philips Digital Interface (SPDIF)
59.1 Overview ......................................................................................................................................................................4841
59.2 External Signals............................................................................................................................................................ 4843
59.3 Clocks........................................................................................................................................................................... 4843
59.4 Functional Description..................................................................................................................................................4843
59.5 SPDIF Memory Map/Register Definition.....................................................................................................................4854
Chapter 60
System Reset Controller (SRC)
60.1 SRC Overview.............................................................................................................................................................. 4873
60.2 External Signals............................................................................................................................................................ 4873
60.3 Clocks........................................................................................................................................................................... 4875
60.4 Top-level resets, power-up sequence and external supply integration......................................................................... 4875
60.5 Power-On Reset and power sequencing....................................................................................................................... 4880
60.6 Functional Description..................................................................................................................................................4881
60.7 SRC Memory Map/Register Definition........................................................................................................................4889
Chapter 61
Synchronous Serial Interface (SSI)
61.1 Overview.......................................................................................................................................................................4909
61.2 External Signal Description.......................................................................................................................................... 4911
61.3 Clocks........................................................................................................................................................................... 4915
61.4 SSI Transmit FIFO 0 & 1 Registers..............................................................................................................................4915
61.5 SSI Transmit Shift Register (TXSR)............................................................................................................................ 4916
61.6 SSI Receive FIFO 0 and 1 Registers.............................................................................................................................4918
61.7 SSI Receive Shift Register (RXSR)..............................................................................................................................4919
61.8 Functional Description..................................................................................................................................................4921
61.9 SSI Memory Map/Register Definition..........................................................................................................................4949
Chapter 62
Temperature Monitor (TEMPMON)
62.1 Overview.......................................................................................................................................................................4981
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Section number Title Page
62.2 Software Usage Guidelines...........................................................................................................................................4982
62.3 TEMPMON Memory Map/Register Definition............................................................................................................4983
Chapter 63
TrustZone Address Space Controller (TZASC)
63.1 Overview.......................................................................................................................................................................4987
63.2 Clocks........................................................................................................................................................................... 4988
63.3 i.MX 6Dual/6Quad Specific Configuration .................................................................................................................4988
63.4 Address Mapping in various memory mapping modes................................................................................................ 4989
Chapter 64
Universal Asynchronous Receiver/Transmitter (UART)
64.1 Overview.......................................................................................................................................................................4991
64.2 External Signals............................................................................................................................................................ 4993
64.3 Clocks........................................................................................................................................................................... 4999
64.4 Functional Description..................................................................................................................................................4999
64.5 Binary Rate Multiplier (BRM)......................................................................................................................................5021
64.6 Infrared Interface.......................................................................................................................................................... 5023
64.7 9-bit RS-485 Mode....................................................................................................................................................... 5028
64.8 Low Power Modes........................................................................................................................................................ 5030
64.9 UART Operation in System Debug State..................................................................................................................... 5032
64.10 Reset..............................................................................................................................................................................5033
64.11 Transfer Error................................................................................................................................................................5033
64.12 Functional Timing.........................................................................................................................................................5034
64.13 Initialization..................................................................................................................................................................5034
64.14 References.....................................................................................................................................................................5037
64.15 UART Memory Map/Register Definition.....................................................................................................................5038
Chapter 65
Universal Serial Bus Controller (USB)
65.1 Overview.......................................................................................................................................................................5069
65.2 External Signals............................................................................................................................................................ 5073
65.3 Functional Description..................................................................................................................................................5074
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