ARM架构参考手册：嵌入式系统开发关键资源

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"ARM架构参考手册，用于嵌入式系统开发，由ARM Limited出版，涵盖从1996年至2005年的多个版本，详细介绍了ARM架构及其使用。" ARM架构参考手册是ARM Limited发布的一份权威技术文档，旨在为嵌入式系统开发者提供全面的ARM处理器架构指南。手册覆盖了从1996年至2005年间更新的内容，展示了ARM技术的发展和改进。这份文档不仅包含了版权信息，还提及了文档版本的更新历史以及ARM公司的商标声明。手册中的"Release Information"部分可能列出了自上一版本以来所做的更改，这些更改可能涉及处理器的新功能、性能提升、错误修复或其他重要更新，确保开发者能了解到最新的技术进展。 "Proprietary Notice"章节明确了ARM的知识产权，包括注册商标和未注册商标的使用规定。例如，ARM、ARMPowered、Thumb、StrongARM等都是ARM Limited的注册商标，而ARM7TDMI、ARM9TDMI等则是其产品系列的标识。此外，手册还指出，所有其他提及的产品或服务可能是各自所有者的商标。文档的核心部分详细介绍了ARM架构，包括其指令集体系结构（ISA）、处理器核心设计、内存管理、中断处理机制、调试接口（如Embedded ICE）以及其他相关技术。这有助于开发者理解如何在硬件层面实现软件代码，并优化应用程序以适应特定的ARM处理器。 ARM架构的许可条款也在文档中提及，通常提供了一种非排他性的、不可转让的、免版税的世界范围内的使用权，允许用户使用此架构信息进行设计和开发。然而，这些许可条件通常会有一些限制，比如不能用于制造与ARM竞争的产品。总体来说，"ARM Architecture Reference Manual"是开发者、工程师和研究人员理解、设计和实现基于ARM架构的嵌入式系统的必备资源。它提供了深入的技术细节，帮助专业人士充分利用ARM处理器的潜力，实现高效、可靠的系统设计。

Preface

• The restriction that multiplication destination registers should be different from their source registers

is removed in ARMv6.

• In ARMv5, the

LDM

(2) and

STM

(2) ARM instructions have restrictions on the use of banked registers

by the immediately following instruction. These restrictions are removed from ARMv6.

• The rules determining which PSR bits are updated by an

MSR

instruction are clarified and extended to

cover the new PSR bits defined in ARMv6.

• In ARMv5, the Thumb

MOV

instruction behavior varies according to the registers used (see note). Two

changes are made in ARMv6.

— The restriction about the use of low register numbers in the

MOV

(3) instruction encoding is

removed.

— In order to make the new side-effect-free

MOV

instructions available to the assembler language

programmer without changing the meaning of existing assembler sources, a new assembler

syntax

CPY Rd,Rn

is introduced. This always assembles to the

MOV

(3) instruction regardless of

whether Rd and Rn are high or low registers.

Note

In ARMv5, the Thumb

MOV Rd,Rn

instructions have the following properties:

• If both Rd and Rn are low registers, the instruction is the

MOV

(2) instruction. This instruction sets the

N and Z flags according to the value transferred, and sets the C and V flags to 0.

• If either Rd or Rn is a high register, the instruction is the

MOV

(3) instruction. This instruction leaves

the condition flags unchanged.

This situation results in behavior that varies according to the registers used. The

MOV

(2) side-effects also limit

compiler flexibility on use of pseudo-registers in a global register allocator.

Naming of ARM/Thumb architecture versions

To name a precise version and variant of the ARM/Thumb architecture, the following strings are

concatenated:

1. The string

ARMv

2. The version number of the ARM instruction set.

3. Variant letters of the included variants.

4. In addition, the letter P is used after x to denote the exclusion of several instructions in the

ARMv5TExP variant.

The table Architecture versions on page xvii lists the standard names of the current (not obsolete)

ARM/Thumb architecture versions described in this manual. These names provide a shorthand way of

describing the precise instruction set implemented by an ARM processor. However, this manual normally

uses descriptive phrases such as T variants of architecture version 4 and above to avoid the use of lists of

architecture names.

Preface

Part B - Memory and System Architectures

Part B describes standard memory system features that are normally implemented by the System Control

coprocessor (coprocessor 15) in an ARM-based system. It contains the following chapters:

Chapter B1 Gives a brief overview of this part of the manual.

Chapter B2 The memory order model.

Chapter B3 Gives a general description of the System Control coprocessor and its use.

Chapter B4 Describes the standard ARM memory and system architecture based on the use of a Virtual

Memory System Architecture (VMSA) based on a Memory Management Unit (MMU).

Chapter B5 Gives a description of the simpler Protected Memory System Architecture (PMSA) based on

a Memory Protection Unit (MPU).

Chapter B6 Gives a description of the standard ways to control caches and write buffers in ARM

memory systems. This chapter is relevant both to systems based on an MMU and to systems

based on an MPU.

Chapter B7 Describes the Tightly Coupled Memory (TCM) architecture option for level 1 memory.

Chapter B8 Describes the Fast Context Switch Extension and Context ID support (ARMv6 only).

Part C - Vector Floating-point Architecture

Part C describes the Vector Floating-point (VFP) architecture. This is a coprocessor extension to the ARM

architecture designed for high floating-point performance on typical graphics and DSP algorithms.

Chapter C1 Gives a brief overview of the VFP architecture and information about its compliance with

the IEEE 754-1985 floating-point arithmetic standard.

Chapter C2 Describes the floating-point formats supported by the VFP instruction set, the floating-point

general-purpose registers that hold those values, and the VFP system registers.

Chapter C3 Describes the VFP coprocessor instruction set, organized by type of instruction.

Chapter C4 Contains detailed reference material on the VFP coprocessor instruction set, organized

alphabetically by instruction mnemonic.

Chapter C5 Contains detailed reference material on the addressing modes used by VFP instructions.

One of these is a traditional addressing mode, generating addresses for load/store

instructions. The remainder specify how the floating-point general-purpose registers and

instructions can be used to hold and perform calculations on vectors of floating-point values.

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